参数资料
型号: MSC1210Y3PAGTG4
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 33 MHz, MICROCONTROLLER, PQFP64
封装: GREEN, PLASTIC, TQFP-64
文件页数: 68/94页
文件大小: 913K
代理商: MSC1210Y3PAGTG4
MSC1210
SBAS203J MARCH 2002 REVISED JANUARY 2008
www.ti.com
70
Serial Port 1 Control (SCON1)
7
6
5
4
3
2
1
0
Reset Value
SFR C0h
SM0_1
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
00h
SM02
Serial Port 1 Mode. These bits control the mode of serial Port 1. Modes 1, 2, and 3 have 1 start and 1 stop bit
bits 75
in addition to the 8 or 9 data bits.
MODE
SM0
SM1
SM2
FUNCTION
LENGTH
PERIOD
0
Synchronous
8 bits
12 pCLK(1)
0
1
Synchronous
8 bits
4 pCLK(1)
1
0
1
0
Asynchronous
10 bits
Timer 1 Baud Rate Equation
1
0
1
Valid Stop Required(2)
10 bits
Timer 1 or Baud Rate Equation
2
1
0
Asynchronous
11 bits
64 pCLK(1) (SMOD = 0)
32 pCLK(1) (SMOD = 1)
2
1
0
1
Asynchronous with Multiprocessor
Communication(3)
11 bits
64 pCLK(1) (SMOD = 0)
32 pCLK(1) (SMOD = 1)
3
1
0
Asynchronous
11 bits
Timer 1 Baud Rate Equation
3
1
Asynchronous with Multiprocessor
Communication(3)
11 bits
Timer 1 Baud Rate Equation
(1) pCLK will be equal to tCLK, except that pCLK will stop for IDLE.
(2) RI_0 will only be activated when a valid STOP is received.
(3) RI_0 will not be activated if bit 9 = 0.
REN_1
Receive Enable. This bit enables/disables the serial Port 1 received shift register.
bit 4
0 = Serial Port 1 reception disabled.
1 = Serial Port 1 received enabled (modes 1, 2, and 3). Initiate synchronous reception (mode 0).
TB8_1
9th Transmission Bit State. This bit defines the state of the 9th transmission bit in serial Port 1 modes 2 and 3.
bit 3
RB8_1
9th Received Bit State. This bit identifies the state of the 9th reception bit of received data in serial Port 1 modes
bit 2
2 and 3. In serial port mode 1, when SM2_1 = 0, RB8_1 is the state of the stop bit. RB8_1 is not used in mode 0.
TI_1
Transmitter Interrupt Flag. This bit indicates that data in the serial Port 1 buffer has been completely shifted out.
bit 1
In serial port mode 0, TI_1 is set at the end of the 8th data bit. In all other modes, this bit is set at the end of the last
data bit. This bit must be cleared by software to transmit the next byte.
RI_1
Receiver Interrupt Flag. This bit indicates that a byte of data has been received in the serial Port 1 buffer. In serial
bit 0
port mode 0, RI_1 is set at the end of the 8th bit. In serial port mode 1, RI_1 is set after the last sample of the incoming
stop bit subject to the state of SM2_1. In modes 2 and 3, RI_1 is set after the last sample of RB8_1. This bit must
be cleared by software to receive the next byte.
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