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| 型号： | MSC7113VM1000 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 32-BIT, 266 MHz, OTHER DSP, PBGA400 |
| 封装： | 17 X 17 MM, LEAD FREE, BGA-400 |
| 文件页数： | 26/60页 |
| 文件大小： | 721K |
| 代理商： | MSC7113VM1000 |
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MSC7113 Data Sheet, Rev. 11
Freescale Semiconductor
32
Figure 14 and Figure 15 show HDI16 read signal timing. Figure 16 and Figure 17 show HDI16 write signal
timing.
Notes:
1.
THCLK = 2/ (Core Clock). At 200 MHz, THCLK = 10 ns. TCORE = core clock period. At 266 MHz, TCORE = 3.75 ns.
2.
In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3.
VDD = 3.3 V ± 0.15 V; TJ = –40°C to +105 °C, CL = 30 pF for maximum delay timings and CL = 0 pF for minimum delay timings.
4.
The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode.
5.
For 64-bit transfers, The “last data register” is the register at address 0x7, which is the last location to be read or written in data
transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).
6.
This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal.
7.
This timing is applicable only if two consecutive reads from one of these registers are executed.
8.
The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
9.
The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe
(HDS/HDS) in the single data strobe mode.
10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host
request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full
(treat as level Host Request).
11. Compute the value using the expression.
12. For mask set 1M88B, the read and write data strobe minimum deassertion width for non-”last data register” accesses in single
and dual data strobe modes is based on timings 57 and 58.
Figure 14. Read Timing Diagram, Single Data Strobe
Table 25. Host Interface (HDI16) Timing1, 2 (continued)
No.
Characteristics3
Mask Set 1L44X
Mask Set 1M88B
Unit
Expression
Value
Expression
Value
HDS
HA[0–3]
HCS[1–2]
HD[0–15]
50
55
44c
44a
53
52
58
57
51
49
61
56
HREQ (single host request)
HRW
57
58
HRRQ (double host request)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC711XADS
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