参数资料
型号: MSC7113VM1000
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 数字信号处理
英文描述: 32-BIT, 266 MHz, OTHER DSP, PBGA400
封装: 17 X 17 MM, LEAD FREE, BGA-400
文件页数: 49/60页
文件大小: 721K
代理商: MSC7113VM1000
Hardware Design Considerations
MSC7113 Data Sheet, Rev. 11
Freescale Semiconductor
53
3.4.3.2
I2C Boot
When the MSC7113 device is configured to boot from the I2C port, the boot program configures the GPIO pins shared with the
I2C pins as I2C pins. The I2C interface is configured as follows:
I2C in master mode.
EPROM in slave mode.
For details on the boot procedure, see the “Boot Program” chapter of the MSC711x Reference Manual.
3.5
DDR Memory System Guidelines
MSC7113 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM
memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are two termination techniques, as shown
in Figure 36. Technique B is the most popular termination technique.
Figure 37 illustrates the power wattage for the resistors. Typical values for the resistors are as follows:
RS = 22
Ω
RT = 24
Ω
Figure 36. SSTL Termination Techniques
Controller
Address
Command
Chip Selects
Data
Strobes
Mask
VREF
VTT
T
e
rm
in
ator
VTT
Generator
DDR
Bank
DDR
Bank
VTT
SSTL_2
RS
RT
RS
Controller
Address
Command
Chip Selects
Data
Strobes
Mask
VT
T
e
rm
ina
tor
I
s
land
VTT
Generator
DDR
Bank
DDR
Bank
SSTL_2
RS
RT
RS
Technique A
Technique B
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:
MSC711XADS
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