参数资料
型号: MSC7116VM800
厂商: Freescale Semiconductor
文件页数: 11/60页
文件大小: 0K
描述: IC DSP PROCESSOR 16BIT 400MAPBGA
标准包装: 90
系列: StarCore
类型: SC1400 内核
接口: 主机接口,I²C,UART
时钟速率: 200MHz
非易失内存: 外部
芯片上RAM: 400kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.20V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 400-LFBGA
供应商设备封装: 400-MAPBGA(17x17)
包装: 托盘
Electrical Characteristics
MSC7116 Data Sheet, Rev. 13
Freescale Semiconductor
19
Table 4 describes thermal characteristics of the MSC7116 for the MAP-BGA package.
Section 3.1, Thermal Design Considerations explains these characteristics in detail.
This section describes the DC electrical characteristics for the MSC7116.
Note:
The leakage current is measured for nominal voltage values must vary in the same direction (for example, both VDDIO
and VDDC vary by +2 percent or both vary by –2 percent).
Table 4. Thermal Characteristics for MAP-BGA Package
Characteristic
Symbol
MAP-BGA 17
× 17 mm5
Unit
Natural
Convection
200 ft/min
(1 m/s) airflow
Junction-to-ambient1, 2
RθJA
39
31
°C/W
Junction-to-ambient, four-layer board1, 3
RθJA
23
20
°C/W
Junction-to-board4
RθJB
12
°C/W
Junction-to-case5
RθJC
7
°C/W
Junction-to-package-top6
ΨJT
2
°C/W
Notes:
1.
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2.
Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3.
Per JEDEC JESD51-6 with the board horizontal.
4.
Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on
the top surface of the board near the package.
5.
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6.
Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
Table 5. DC Electrical Characteristics
Characteristic
Symbol
Min
Typical
Max
Unit
Core and PLL voltage
VDDC
VDDPLL
1.14
1.2
1.26
V
DRAM interface I/O voltage1
VDDM
2.375
2.5
2.625
V
I/O voltage
VDDIO
3.135
3.3
3.465
V
DRAM interface I/O reference voltage2
VREF
0.49
× VDDM
1.25
0.51
× VDDM
V
DRAM interface I/O termination voltage3
VTT
VREF – 0.04
VREF
VREF + 0.04
V
Input high CLKIN voltage
VIHCLK
2.4
3.0
3.465
V
DRAM interface input high I/O voltage
VIHM
VREF + 0.28
VDDM
VDDM + 0.3
V
DRAM interface input low I/O voltage
VILM
–0.3
GND
VREF – 0.18
V
Input leakage current, VIN = VDDIO
IIN
–1.0
0.09
1
A
VREF input leakage current
IVREF
——
5
A
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