参数资料
型号: MSC8101VT1375F
厂商: Freescale Semiconductor
文件页数: 12/104页
文件大小: 0K
描述: IC DSP 16BIT 250MHZ 332-FCPBGA
标准包装: 90
系列: StarCore
类型: SC140 内核
接口: 通信处理器模块(CPM)
时钟速率: 275MHz
非易失内存: 外部
芯片上RAM: 512kB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.60V
工作温度: -40°C ~ 105°C
安装类型: 表面贴装
封装/外壳: 332-BFBGA,FCPBGA
供应商设备封装: 332-FCBGA(17x17)
包装: 托盘
System Bus, HDI16, and Interrupt Signals
MSC8101 Technical Data, Rev. 19
Freescale Semiconductor
1-11
IRQ1
DP1
EXT_BG2
Input
Input/Output
Output
Interrupt Request 11
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Data Parity 11
The agent that drives the data bus also drives the data parity signals. The value driven on the data
parity one pin should give odd parity (odd number of ones) on the group of signals that includes data
parity 1 and D[8–15].
External Bus Grant 21,2
The MSC8101 asserts this pin to grant bus ownership to an external bus master.
IRQ2
DP2
EXT_DBG2
Input
Input/Output
Output
Interrupt Request 21
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Data Parity 21
The agent that drives the data bus also drives the data parity signals. The value driven on the data
parity two pin should give odd parity (odd number of ones) on the group of signals that includes data
parity 2 and D[16–23].
External Data Bus Grant 21,2
The MSC8101 asserts this pin to grant data bus ownership to an external bus master.
IRQ3
DP3
EXT_BR3
Input
Input/Output
Input
Interrupt Request 31
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Data Parity 31
The agent that drives the data bus also drives the data parity signals. The value driven on the data
parity three pin should give odd parity (odd number of ones) on the group of signals that includes
data parity 3 and D[24–31].
External Bus Request 31,2
An external master asserts this pin to request bus ownership from the internal arbiter.
IRQ4
DP4
DREQ3
EXT_BG3
Input
Input/Output
Input
Output
Interrupt Request 41
One of eight external lines that can request a service routine, via the internal interrupt controller,
from the SC140 core.
Data Parity 41
The agent that drives the data bus also drives the data parity signals. The value driven on the data
parity four pin should give odd parity (odd number of ones) on the group of signals that includes data
parity 4 and D[32–39].
DMA Request 31
An external peripheral uses this pin to request DMA service.
External Bus Grant 31,2
The MSC8101 asserts this pin to grant bus ownership to an external bus master.
Table 1-5.
System Bus, HDI16, and Interrupt Signals (Continued)
Signal
Data Flow
Description
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