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参数资料
| 型号： | MSC8126TMP6400 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 数字信号处理 |
| 英文描述： | 0-BIT, 400 MHz, OTHER DSP, PBGA431 |
| 封装： | 20 X 20 MM, PLASTIC, FCBGA-431 |
| 文件页数： | 16/48页 |
| 文件大小： | 1138K |
| 代理商： | MSC8126TMP6400 |
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Electrical Characteristics
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 15
Freescale Semiconductor
23
The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller configuration.
The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only on the REFCLK rising edge.
Table 14. AC Timing for SIU Inputs
No.
Characteristic
Value for Bus Speed in MHz
Units
Ref = CLKIN
Ref =
CLKOUT
133
166
133
10
Hold time for all signals after the 50% level of the REFCLK rising edge
0.5
ns
11a
ARTRY/ABB set-up time before the 50% level of the REFCLK rising
edge
3.0
ns
11b
DBG/DBB/BG/BR/TC set-up time before the 50% level of the
REFCLK rising edge
3.3
ns
11c
AACK set-up time before the 50% level of the REFCLK rising edge
2.9
ns
11d
TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK
rising edge
Data-pipeline mode
Non-pipeline mode
3.4
4.0
3.4
4.0
3.4
4.0
ns
12
Data bus set-up time before REFCLK rising edge in Normal mode
Data-pipeline mode
Non-pipeline mode
1.8
4.0
1.7
4.0
1.8
4.0
ns
131
Data bus set-up time before the 50% level of the REFCLK rising edge
in ECC and PARITY modes
Data-pipeline mode
Non-pipeline mode
2.0
7.3
2.0
7.3
2.0
7.3
ns
141
DP set-up time before the 50% level of the REFCLK rising edge
Data-pipeline mode
Non-pipeline mode
2.0
6.1
2.0
6.1
2.0
6.1
ns
15a
TS and Address bus set-up time before the 50% level of the REFCLK
rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
3.6
5.0
3.6
5.0
3.8
5.0
ns
15b
Address attributes: TT/TBST/TSZ/GBL set-up time before the 50%
level of the REFCLK rising edge
Extra cycle mode (SIUBCR[EXDD] = 0)
No extra cycle mode (SIUBCR[EXDD] = 1)
3.5
4.4
3.5
4.4
3.5
4.4
ns
16
PUPMWAIT signal set-up time before the 50% level of the REFCLK
rising edge
3.7
ns
17
IRQx setup time before the 50% level; of the REFCLK rising edge3
4.0
ns
18
IRQx minimum pulse width3
6.0 + TREFCLK
ns
Notes:
1.
Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.
2.
Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.
3.
Guaranteed by design
Table 15. AC Timing for SIU Outputs
No.
Characteristic
Value for Bus Speed in MHz
Units
Ref = CLKIN
Ref = CLKOUT
133
166
133
302
Minimum delay from the 50% level of the REFCLK for all signals
0.8
1.0
ns
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