参数资料
型号: MSC8144VT800A
厂商: Freescale Semiconductor
文件页数: 62/80页
文件大小: 0K
描述: IC DSP QUAD 800MHZ 783FCBGA
标准包装: 1
系列: StarCore
类型: SC3400 内核
接口: 以太网,I²C,SPI,TDM,UART,UTOPIA
时钟速率: 800MHz
非易失内存: 外部
芯片上RAM: 10.5MB
电压 - 输入/输出: 3.30V
电压 - 核心: 1.00V
工作温度: 0°C ~ 90°C
安装类型: 表面贴装
封装/外壳: 783-BBGA,FCBGA
供应商设备封装: 783-FCPBGA(29x29)
包装: 托盘
Hardware Design Considerations
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
65
The following supplies should rise before any other supplies in any sequence
VDD and VDDPLL coupled together
VDDM3
After the above supplies rise to 90% of their nominal value the following I/O supplies may rise in any sequence (see Figure 42):
VDDGE1
VDDGE2
VDDIO
VDDDDR and MVREF coupled one to another. MVREF should be either at same time or after VDDDDR.
VDDM3IO
V25M3
Note:
1.
This recommended power sequencing is different from the MSC8122/MSC8126.
2.
If no pins that require VDDGE1 as a reference supply are used (see Table 1), VDDGE1 can be tied to GND.
3.
If no pins that require VDDGE2 as a reference supply are used (see Table 1), VDDGE2 can be tied to GND.
4.
If the DDR interface is not used, VDDDDR and MVREF can be tied to GND.
5.
If the M3 memory is not used, VDDM3, VDDM3IO, and V25M3 can be tied to GND.
6.
If the RapidIO interface is not used, VDDSX, VDDSXP, and VDDRIOPLL can be tied to GND.
3.1.2
Start-Up Timing
Section 2.6.1 describes the start-up timing.
Figure 42. VDDM3, VDDM3IO and V25M3 Power-on Sequence
VDDM3, VDD, and VDDPLL
90%
I/O supplies
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