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17
MSM66587 Family User's Manual
Chapter 17 Interrupt Request Processing
17.3
Maskable Interrupt Operation
Generation of an interrupt signal causes an interrupt request to be passed to interrupt priority
selection logic by the following operation.
An interrupt request signal is output from the interrupt source.
When the IRQ bit becomes "1", if either the corresponding IE bit or MIE in PSW is "1", then
the interrupt will be held off. When the IRQ bit becomes "1", if both the corresponding IE bit
and MIE in PSW is "1", then the interrupt priority selection logic will operate.
The interrupt priority selection logic operates as follows.
If MIP in PSW is "0", then the interrupt priority selection logic will not operate, and the interrupt
will be generated immediately. If MIP in PSW is "1", then the interrupt will be given a priority
from one of three levels (level 0 to level 2) by the corresponding IPX0 and IPX1 bits.
If no other interrupt is being executed at the time the interrupt request is sent to the interrupt
priority selection logic, then the interrupt will be generated immediately.
If one or more other interrupts are already being executed at the time the interrupt request
is sent to the interrupt priority selection logic, and if the new interrupt has a higher priority level
than any of the executing interrupts, then the interrupt will be generated immediately.
If one or more other interrupts are already being executed at the time the interrupt request
is sent to the interrupt priority selection logic, and if the new interrupt has a lower priority level
than any of the executing interrupts, then the interrupt will be held off.
Generated
Interrupt
Process
Being Executed
Level 0 Interrupt
Request
m
: Interrupt generated
Level 1 Interrupt
Request
Level 2 Interrupt
Request
NMI Interrupt
Request
No interrupt process
m
: Interrupt generated
m
: Interrupt generated m : Interrupt generated
: Interrupt held
Level 0 interrupt process
m
: Interrupt generated
m
: Interrupt generated m : Interrupt generated
: Interrupt held
Level 1 interrupt process
: Interrupt held
m
:Interrupt generated
m
: Interrupt generated
: Interrupt held
Level 2 interrupt process
: Interrupt held
m
: Interrupt generated
: Interrupt held
NMI interrupt process
: Interrupt held
Note:
When interrupts are generated simultaneously, the one with higher priority will have
precedence. When interrupts of the same priority are generated simultaneously, the one
with the lower interrupt vector address will have precedence.