参数资料
型号: MSM80C88A-10
厂商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 8-Bit CMOS Microprocessor(内部结构为16位,外围接口8位,8位微处理器)
中文描述: 8位CMOS微处理器(内部结构为16位,外围接口8位,8位微处理器)
文件页数: 15/37页
文件大小: 270K
代理商: MSM80C88A-10
15/37
Semiconductor
MSM80C88A-10RS/GS/JS
PIN DESCRIPTION
AD
0
- AD
7
ADDRESS DATA BUS: Input/Output
These lines are the multiplexed address and data bus.
These are the address bus at T
1
cycle and the data bus at T
2
, T
3
, T
W
and T
4
cycle.
T
2
, T
3
, T
W
and T
4
cycle.
These lines are high impedance during interrupt acknowledge and hold acknowledge.
A
8
- A
15
ADDRESS BUS: Output
These lines are the address bus bits 8 thru 15 at all cycles.
These lines do not have to be latched by an ALE signal.
These lines are high impedance during interrupt acknowledge and hold acknowledge.
A
16
/S
3
, A
17
/S
4
, A
18
/S
5
, A
19
/S
6
ADDRES/STATUS : Output
These are the four most significant address as at the T
1
, cycle.
Accessing I/O port address, these are low at T
1
Cycle.
These lines are Status lines at the T
2
, T
3
, T
W
and T
4
Cycles.
S
5
indicates interrupt enable Flag.
S
3
and S
4
are encoded as shown below.
These lines are high impedance during hold acknowledge.
RD
READ: Output
This line indicates that CPU is in a memory or I/O read cycle.
This line is the read strobe signal when CPU reads data from a memory or I/O device. This
line is active low.
This line is high impedance during hold acknowledge.
READY
READY:Input
This line indicates to the CPU that the addressed memory or I/O device is ready to read or
write.
This line is active high. If the setup and hold time are out of specification, an illegal operation
will occur.
INTR
INTERRUPT REQUEST: Input
This line is the level triggered interrupt request signal which is sampled during the last clock
cycle of instruction and string manipulations.
It can be internally masked by software.
This signal is active high and internally synchronized.
1
0
1
Stack
Code or None
Data
0
Alternate Data
S
3
0
1
1
0
S
4
Characteristics
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