参数资料
型号: MSM80C88A-10
厂商: OKI SEMICONDUCTOR CO., LTD.
英文描述: 8-Bit CMOS Microprocessor(内部结构为16位,外围接口8位,8位微处理器)
中文描述: 8位CMOS微处理器(内部结构为16位,外围接口8位,8位微处理器)
文件页数: 9/37页
文件大小: 270K
代理商: MSM80C88A-10
9/37
Semiconductor
MSM80C88A-10RS/GS/JS
Timing Responses
Parameter
Symbol
Unit
Max.
35
45
Min.
5
5
10 MHz Spec.
V
CC
= 4.75 V to 5.25 V
Ta = 0 to +70°C
Max.
35
45
Min.
5
5
8 MHz Spec.
V
CC
= 4.75 V to 5.25 V
Ta = 0 to +70°C
Max.
45
45
Min.
5
5
5 MHz Spec.
V
CC
= 4.5 V to 5.5 V
Ta = –40 to +85°C
Command Active Delay (See Note 1)
Command Inactive Delay (See Note 1)
READY Active to Status Passive
(See Note 4)
Status Active Delay
t
CLML
t
CLMH
ns
ns
t
RYHSH
45
ns
65
110
Status Inactive Delay
Address Valid Delay
Address Hold Time
Address Float Delay
Status Valid to ALE High (See Note 1)
Status Valid to MCE High (See Note 1)
CLK Low to ALE Valid (See Note 1)
CLK Low to MCE High (See Note 1)
ALE Inactive Delay (See Note 1)
Data Valid Delay
Data Hold Time
Control Active Delay (See Note 1)
Control Inactive Delay (See Note 1)
Address Float to
RD
Active
t
CHSV
t
CLSH
t
CLAV
t
CLAX
t
CLAZ
t
SVLH
t
SVMCH
t
CLLH
t
CLMCH
t
CHLL
t
CLDV
t
CHDX
t
CVNV
t
CVNX
t
AZRL
t
CLRL
t
CLRH
t
RHAV
10
10
10
10
t
CLAX
4
10
10
5
5
0
10
10
t
CLCL
-35
45
60
60
50
25
30
25
25
25
60
45
45
70
60
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
10
10
10
t
CLAX
4
10
10
5
5
0
10
10
t
CLCL
-40
60
70
60
50
25
30
25
25
25
60
45
45
100
80
10
10
10
10
t
CLAX
4
10
10
5
5
0
10
10
t
CLCL
-45
110
130
110
80
35
35
35
35
35
110
45
45
165
150
RD
Active Delay
RD
Inactive Delay
RD
Inactive to Next Address Active
Direction Control Active Delay
(See Note 1)
Direction Control Inactive Delay
(See Note 1)
t
CHDTL
50
ns
50
50
GT
Active Delay (See Note 5)
GT
Inactive Delay
RD
Width
Output Rise Time (From 0.8 V to 2.0 V)
Output Fall Time (From 2.0 V to 0.8 V)
t
CLGL
t
CLGH
t
RLRH
t
OLOH
t
OHOL
0
0
45
45
15
15
ns
ns
ns
ns
ns
0
0
50
50
15
15
0
0
85
85
15
15
2t
CLCL
-40
2t
CLCL
-50
2t
CLCL
-75
t
CHDTH
30
ns
30
35
Notes: 1. Signals at MSM82C84A-2 or MSM82C88-2 are shown for reference only.
2. Setup requirement for asynchronous signal only to guarantee recognition at next
CLK.
3. Applies only to T
2
state (8 ns into T
3
)
4. Applies only to T
3
and wait states.
5. C
L
= 40 pF (
RQ
/
GT
0
,
RQ
/
GT
1
)
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