参数资料
型号: MSP430F5634IZQW
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PBGA113
封装: GREEN, PLASTIC, BGA-113
文件页数: 51/101页
文件大小: 1073K
代理商: MSP430F5634IZQW
PRODUCTPREVIEW
t
SU,MI
t
HD,MI
UCLK
SOMI
SIMO
t
VALID,MO
t
HD,MO
CKPL =0
CKPL =1
t
LO/HI
t
LO/HI
1/f
UCxCLK
MSP430F563x
www.ti.com
SLAS650A – JUNE 2010 – REVISED JULY 2010
USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
(see Note
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
SMCLK, ACLK
fUSCI
USCI input clock frequency
fSYSTEM
MHz
Duty cycle = 50% ± 10%
1.8 V
55
PMMCOREV = 0
ns
3 V
38
tSU,MI
SOMI input data setup time
2.4 V
30
PMMCOREV = 3
ns
3 V
25
1.8 V
0
PMMCOREV = 0
ns
3 V
0
tHD,MI
SOMI input data hold time
2.4 V
0
PMMCOREV = 3
ns
3 V
0
UCLK edge to SIMO valid,
1.8 V
20
CL = 20 pF
ns
3 V
18
PMMCOREV = 0
tVALID,MO
SIMO output data valid time(2)
UCLK edge to SIMO valid,
2.4 V
16
CL = 20 pF
ns
3 V
15
PMMCOREV = 3
1.8 V
-10
CL = 20 pF
ns
PMMCOREV = 0
3 V
-8
tHD,MO
SIMO output data hold time(3)
2.4 V
-10
CL = 20 pF
ns
PMMCOREV = 3
3 V
-8
(1)
fUCxCLK = 1/2tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave)).
For the slave's parameters tSU,SI(Slave) and tVALID,SO(Slave) refer to the SPI parameters of the attached slave.
(2)
Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 3 and Figure 4.
(3)
Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 3. SPI Master Mode, CKPH = 0
Copyright 2010, Texas Instruments Incorporated
53
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