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参数资料
型号： MSP430F5634IZQW
厂商： TEXAS INSTRUMENTS INC
元件分类： 微控制器/微处理器
英文描述： 16-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PBGA113
封装： GREEN, PLASTIC, BGA-113
文件页数： 62/101页
文件大小： 1073K
代理商： MSP430F5634IZQW
PRODUCTPREVIEW
MSP430F563x
www.ti.com
SLAS650A – JUNE 2010 – REVISED JULY 2010
12-bit DAC, Reference Input Specifications
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
AVCC/
AVCC
DAC12IR = 0(1) (2)
3
+ 0.2
VeREF+
Reference input voltage range
2.2 V/3 V
V
AVCC
DAC12IR = 1(3) (4)
AVCC
+ 0.2
DAC12_0 IR = DAC12_1 IR = 0
20
M
DAC12_0 IR = 1, DAC12_1 IR = 0
48
Ri(VREF+),
DAC12_0 IR = 0, DAC12_1 IR = 1
48
Reference input resistance(5)
2.2 V/3 V
Ri(VeREF+)
k
DAC12_0 IR = DAC12_1 IR = 1,
DAC12_0 SREFx = DAC12_1
24
SREFx(6)
(1)
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
(2)
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
(3)
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
(4)
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
(5)
This impedance depends on tradeoff in power savings. Current devices have 48 k
for each channel when divide is enabled. Can be
increased if performance can be maintained.
(6)
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel
reducing the reference input resistance.
12-bit DAC, Dynamic Specifications
VREF = VCC, DAC12IR = 1 (see Figure 11 and Figure 12)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
DAC12AMPx = 0
→ {2,
60
120
3, 4}
DAC12_xDAT = 800h,
tON
DAC12 on time
ErrorV(O) < ±0.5 LSB
(1)
DAC12AMPx = 0
→ {5,
2.2 V/3 V
s
15
30
(see Figure 11)
6}
DAC12AMPx = 0
→ 7
6
12
DAC12AMPx = 2
100
200
DAC12_xDAT =
tS(FS)
Settling time, full scale
DAC12AMPx = 3, 5
2.2 V/3 V
40
80
s
80h
→ F7Fh → 80h
DAC12AMPx = 4, 6, 7
15
30
DAC12AMPx = 2
5
DAC12_xDAT =
tS(C-C)
Settling time, code to code
3F8h
→ 408h → 3F8h,
DAC12AMPx = 3, 5
2.2 V/3 V
2
s
BF8h
→ C08h → BF8h
DAC12AMPx = 4, 6, 7
1
DAC12AMPx = 2
0.05
0.35
DAC12_xDAT =
SR
Slew rate
DAC12AMPx = 3, 5
2.2 V/3 V
0.35
1.10
V/s
80h
→ F7Fh → 80h(2)
DAC12AMPx = 4, 6, 7
1.50
5.20
DAC12_xDAT =
Glitch energy
DAC12AMPx = 7
2.2 V/3 V
35
nV-s
800h
→ 7FFh → 800h
(1)
RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 11.
(2)
Slew rate applies to output voltage steps
≥ 200 mV.
Copyright 2010, Texas Instruments Incorporated
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