参数资料
型号: MSX532
元件分类: 数字信号处理外设
英文描述: DSP-CROSSBAR SWITCH, PBGA792
封装: PLASTIC, BGA-792
文件页数: 3/5页
文件大小: 139K
代理商: MSX532
MSX532 Mini Data Sheet- Matrix Switching Crossbar Device
I-Cube, Inc.
Last Modified: 11/8/99
Page 3
PRELIMINARY
Symbol
I/O Port Function
Px
Ax
IE
Input - The external signal is buffered from the I/O Port pin to the corresponding Switch Matrix line. In
this mode an optional input enable (IE) can be selected.
Px
Ax
OE
Output - The internal signal is buffered from the corresponding Switch Matrix line to the I/O Port pin. In
this mode an optional output enable (OE*) can be selected. The default level is logic 0.
The output data inversion mode is available to invert the output signal.
DQ
Px
Ax
IE
CLK
Registered Input - A clock source is required in this mode. An input enable (IE) is available but not
required.
DQ
CLK
Px
Ax
OE
Registered Output – The internal signal on the Switch Matrix line is registered by an edge-triggered flip-
flop within the I/O Port. A clock source is required in this mode. An output enable (OE*) is available but
not required.
The output data inversion mode is available to invert the output signal.
Px
Ax
IE
OE
Bidirectional Transceiver - In this mode, the I/O buffer acts as a bidirectional transceiver between the
I/O Port pin and the corresponding Switch Matrix line. This mode requires an input enable (IE) and
output enable (OE). When the same source is used for IE and OE, it effectively acts as direction control.
When the same control signal (with one polarity inverted) is used for IE and OE, it effectively acts as a
Bus Repeater (BR) (see below) when both are enabled, and as No Connect (NC) when neither is
enabled.
Px
Ax
Bus Repeater - In the Bus Repeater mode, the I/O Port behaves as a wire (with a non-zero propagation
delay). This unique feature patented by I-Cube, Inc. as self-sensing circuit to determine signal direction
and does not require a direction control signal.
When multiple I/O Ports, configured as "Bus Repeater", are connected together through the Switch
Matrix to form a single internal node, an (open collector or tristatable) external signal appearing at any
one of the I/O Ports gets repeated (or broadcast) to other I/O Ports. For more details, refer to the
Technical Note: "The Bus Repeater Mode"
Px
Ax
Pin side force 0 - In this output mode, the I/O Port pin is forced low (logic 0), regardless of the signal on
the corresponding switch Matrix line. In this mode an optional output enable (OE*) can be selected.
Px
Ax
Pin side Force 1 - In this output mode, the I/O Port pin is forced high (logic 1), regardless of the signal
on the corresponding Switch Matrix line. In this mode an optional output enable (OE*) can be selected.
Px
Ax
No Connect - In this mode, the I/O Port pin is isolated from the Switch Matrix. This is done by tri-stating
both the input and output part of the I/O buffer.
Px
Ax
Array Side Force 0 - In this input mode, the Switch Matrix line is forced low (logic 0), regardless of the
signal on the corresponding I/O Port. In this mode an optional input enable (IE) can be selected.
Px
Ax
Array Side Force 1 - In this input mode, the Switch Matrix line is forced high (logic 1), regardless of the
signal on the corresponding I/O Port. In this mode an optional input enable (IE) can be selected.
Table 1: Summary of Programmable I/O Attributes for MSX Devices
Px
Ax
Px
Ax
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