参数资料
型号: MT9D131C12STC
厂商: Aptina LLC
文件页数: 13/18页
文件大小: 0K
描述: SENSOR IMAGE 2MP CMOS 48-CLCC
标准包装: 96
象素大小: 2.8µm x 2.8µm
有源象素阵列: 1600H x 1200V
每秒帧数: 15
电源电压: 2.5 V ~ 3.1 V
类型: CMOS 成像
封装/外壳: 48-CLCC
供应商设备封装: 48-CLCC
包装: 托盘
请注意: *
产品目录页面: 739 (CN2011-ZH PDF)
配用: 557-1253-ND - KIT HEAD BOARD FOR MT9D131
557-1248-ND - KIT DEV FOR MT9D131
其它名称: 557-1311
Preliminary
MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor
Architecture Overview
Figure 6:
Sensor Core Block Diagram
Active-Pixel Sensor
(APS) Array
UXGA
1600H x 1200V
Analog Processing
Control Register
Timing and Control
ADC
Serial
I/O
Sync
Signals
Data
Out
The core of the sensor is an active-pixel array. The timing and control circuitry
sequences through the rows of the array, resetting and then reading each row. In the
time interval between resetting a row and reading that row, the pixels in that row inte-
grate incident light. The exposure is controlled by varying the time interval between
reset and readout. After a row is read, the data from the columns is sequenced through
an analog signal chain (providing offset correction and gain), and then through an ADC.
The output from the ADC is a 10-bit value for each pixel in the array. The pixel array con-
tains optically active and light-shielded “black” pixels. The black pixels are used to pro-
vide data for on-chip offset correction algorithms (black level control).
Die Outline
Figure 7:
Optical Center Offset
8199.35 μ m
( b are d ie)
PLL
First C lear Pixel
( C ol 52, Row 20)
Opti c al C enter
(1 6 7.84 μ m, 2.0 6 μ m)
Die C enter
(0 μ m, 0 μ m)
Last C lear Pixel
( C ol 1 6 83, Row 1235)
Note:
Figure not to scale.
PDF: 09005aef824c90ce/Source: 09005aef824c90d6
MT9D131_LDS_2.fm - Rev. B 3/07 EN
13
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
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相关代理商/技术参数
参数描述
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