参数资料
型号: MT9D131C12STC
厂商: Aptina LLC
文件页数: 4/18页
文件大小: 0K
描述: SENSOR IMAGE 2MP CMOS 48-CLCC
标准包装: 96
象素大小: 2.8µm x 2.8µm
有源象素阵列: 1600H x 1200V
每秒帧数: 15
电源电压: 2.5 V ~ 3.1 V
类型: CMOS 成像
封装/外壳: 48-CLCC
供应商设备封装: 48-CLCC
包装: 托盘
请注意: *
产品目录页面: 739 (CN2011-ZH PDF)
配用: 557-1253-ND - KIT HEAD BOARD FOR MT9D131
557-1248-ND - KIT DEV FOR MT9D131
其它名称: 557-1311
Preliminary
MT9D131: 1/3.2-Inch 2-Mp SOC Digital Image Sensor
Signal Description
Signal Description
Table 3:
Signal Description
Name
EXTCLK
RESET#
STANDBY
TEST
CLCC Pin
40
39
38
20
Type
Input
Input
Input
Input
Description
Master clock signal (can either drive the on-chip PLL or bypass it).
Master reset signal, active LOW.
Controls sensor’s standby mode.
Reserved for factory test. Tie to digital ground during normal
operation.
SCLK
S ADDR
34
35
Input
Input
Two-wire serial interface clock.
Selects device address for the two-wire serial interface. The
address is 0x90 when S ADDR is tied LOW, 0xBA if tied HIGH. See
also R0x0D:0[10].
D OUT [7:0]
FRAME_VALID
LINE_VALID
PIXCLK
8, 9, 10, 11, 14, 15, 16,
17
1
48
47
Input
Input
Input
Input
Eight-bit image data output or most significant bits (MSB) of 10-
bit sensor bypass mode.
Identifies rows in the active image.
Identifies lines in the active image.
Pixel clock. To be used for sampling D OUT , FRAME_VALID, and
LINE_VALID.
S DATA
V DD
V DD PLL
V AA
VAAPIX
V DD Q
A GND
D GND
46
2, 3, 12, 24, 25, 36
41
32, 33
26, 27
21, 22, 44, 5
29, 30, 31
4, 6, 7, 13, 18, 19, 23,
I/O
Supply
Supply
Supply
Supply
Supply
Supply
Supply
Two-wire serial interface data.
Digital power (1.8V).
PLL power (2.8V).
Analog power (2.8V).
Pixel array power (2.8V).
I/O power (nominal 1.8V or 2.8V).
Analog ground.
Digital, I/O, and PLL ground.
28, 37, 42, 43, 45
PDF: 09005aef824c90ce/Source: 09005aef824c90d6
MT9D131_LDS_2.fm - Rev. B 3/07 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2006 Micron Technology, Inc. All rights reserved.
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