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参数资料
| 型号： | MTB36N06VT4 |
| 厂商： | MOTOROLA INC |
| 元件分类： | JFETs |
| 英文描述： | 32 A, 60 V, 0.04 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封装： | D2PAK-3 |
| 文件页数： | 1/10页 |
| 文件大小： | 241K |
| 代理商： | MTB36N06VT4 |
1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's Data Sheet
TMOS V
Power Field Effect Transistor
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
TMOS V is a new technology designed to achieve an on–resistance
area product about one–half that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS E–FET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
New Features of TMOS V
On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology
Faster Switching than E–FET Predecessors
Features Common to TMOS V and TMOS E–FETs
Avalanche Energy Specified
IDSS and VDS(on) Specified at Elevated Temperature
Static Parameters are the Same for both TMOS V and
TMOS E–FET
Surface Mount Package Available in 16 mm 13–inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
60
Vdc
Drain–to–Gate Voltage (RGS = 1.0 M)
VDGR
60
Vdc
Gate–to–Source Voltage — Continuous
Gate–Source Voltage
— Non–Repetitive (tp ≤ 50 s)
VGS
VGSM
±20
±25
Vdc
Vpk
Drain Current — Continuous @ 25
°C
Drain Current — Continuous @ 100
°C
Drain Current — Single Pulse (tp ≤ 10 s)
ID
IDM
32
22.6
112
Adc
Apk
Total Power Dissipation @ 25
°C
Derate above 25
°C
Total Power Dissipation @ TA = 25°C (1)
PD
90
0.6
3.0
Watts
W/
°C
Watts
Operating and Storage Temperature Range
TJ, Tstg
– 55 to 175
°C
Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 32 Apk, L = 0.1 mH, RG = 25 )
EAS
205
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
R
θJC
R
θJA
R
θJA
1.67
62.5
50
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
″ from Case for 10 seconds
TL
260
°C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
REV 2
Order this document
by MTB36N06V/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
TM
MTB36N06V
TMOS POWER FET
32 AMPERES
60 VOLTS
RDS(on) = 0.04 OHM
CASE 418B–02, Style 2
D2PAK
D
S
G
Motorola Preferred Device
Motorola, Inc. 1996
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