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参数资料
| 型号： | MTB3N100E |
| 厂商： | ON SEMICONDUCTOR |
| 元件分类： | JFETs |
| 英文描述： | 3 A, 1000 V, 4 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 文件页数： | 1/10页 |
| 文件大小： | 262K |
| 代理商： | MTB3N100E |
1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltage–blocking capability without degrading perfor-
mance over time. In addition, this advanced TMOS E–FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high
voltage, high speed switching applications in power supplies,
converters and PWM motor controls, these devices are particularly
well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–Source Voltage
VDSS
1000
Vdc
Drain–Gate Voltage (RGS = 1.0 M)
VDGR
1000
Vdc
Gate–Source Voltage — Continuous
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 40
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100
°C
Drain Current — Single Pulse (tp ≤ 10 s)
ID
IDM
3.0
2.4
9.0
Adc
Apk
Total Power Dissipation
Derate above 25
°C
Total Power Dissipation @ TA = 25°C, when mounted with the minimum recommended pad size
PD
125
1.0
2.5
Watts
W/
°C
Watts
Operating and Storage Temperature Range
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 7.0 Apk, L = 10 mH, RG = 25 )
EAS
245
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size
R
θJC
R
θJA
R
θJA
1.0
62.5
50
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
″ from case for 10 seconds
TL
260
°C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
Order this document
by MTB3N100E/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MTB3N100E
TMOS POWER FET
3.0 AMPERES
1000 VOLTS
RDS(on) = 4.0 OHM
Motorola Preferred Device
CASE 418B–02, Style 2
D2PAK
D
S
G
Motorola, Inc. 1995
REV 2
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