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参数资料
| 型号： | MTB8N50ET4 |
| 厂商： | MOTOROLA INC |
| 元件分类： | JFETs |
| 英文描述： | 8 A, 500 V, 0.8 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 文件页数： | 1/6页 |
| 文件大小： | 162K |
| 代理商： | MTB8N50ET4 |
1
Motorola TMOS Power MOSFET Transistor Device Data
Designer's Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltage–blocking capability without degrading perfor-
mance over time. In addition, this advanced TMOS E–FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. This new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters, PWM motor controls, these devices are particularly well
suited for bridge circuits where diode speed and commutating safe
operating areas are critical and offer additional safety margin
against unexpected voltage transients.
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable
to a Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured – Not Sheared
Specifically Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS
500
Vdc
Drain–to–Gate Voltage (RGS = 1.0 MW)
VDGR
500
Vdc
Gate–to–Source Voltage – Continuous
Gate–to–Source Voltage – Non–repetitive (tp
≤ 10 ms)
VGS
VGSM
±20
±40
Vdc
Vpk
Drain Current — Continuous @ TC = 25°C
Drain Current — Continuous @ TC = 100°C
Drain Current — Single Pulse (tp
≤ 10 ms)
ID
IDM
8.0
5.0
32
Adc
Apk
Total Power Dissipation @ TC = 25°C
Derate above 25
°C
PD
125
1.0
Watts
W/
°C
Operating and Storage Temperature Range
TJ, Tstg
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy – STARTING TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 8.0 Apk, L = 16 mH, RG = 25 W)
EAS
510
mJ
Thermal Resistance
– Junction–to–Case
– Junction–to–Ambient
– Junction–to–Ambient (1)
RqJC
RqJA
1.0
62.5
50
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8
″ from Case for 5 sec.
TL
260
°C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 1
Order this document
by MTB8N50E/D
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
MTB8N50E
TMOS POWER FET
8.0 AMPERES
500 VOLTS
RDS(on) = 0.8 OHM
CASE 418B–02, Style 2
D2PAK
D
S
G
Motorola, Inc. 1996
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