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参数资料
| 型号： | MTC311 |
| 厂商： | OKI SEMICONDUCTOR CO., LTD. |
| 英文描述： | PC-ATA Solid State Disk Card(微机异步通信终端适配器的固态磁盘卡) |
| 中文描述： | 电脑- ATA固态硬盘机卡（微机异步通信终端适配器的固态磁盘卡） |
| 文件页数： | 12/45页 |
| 文件大小： | 241K |
| 代理商： | MTC311 |
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9
Semiconductor
MTC311XX-XXX-01
5.1.2 Description of Signals
A description of each signal line for the PCMCIA interface is listed below.
*
Set as a memory card interface immediately after power is switched on or after a reset.
Signal Name
(Input or Output)
–CD1, –CD2
(Output)
D15–D0
(Bidirectional)
–IOWR (Input)
–IORD (Input)
–WE (Input)
–OE (Input)
+RDY/–BSY/–IREQ
(Output)
–CD1 and –CD2 are connected on the card to GND. By using 10k
W
or larger resistors to
pull up these signals, the system can detect whether or not the card has been inserted or removed.
16-bit data bus. D15 is the MSB and D0 is the LSB.
I/O write strobe. Generated when data is written to the ATA register.
I/O read strobe. Generated when data is read from the ATA register.
Memory write enable strobe.
Memory output enable strobe.
During power-on and reset, the BSY signal is active while initialization processing is being
performed on the card.
Thereafter, if the card configuration is set as an I/O card, this signal can be used as an
interrupt signal.
These signals are used when selecting I/O ports (attribute memory address, common memory
address, I/O address) internal to the card.
Card enable signals.
–CE1 controls even addresses and –CE2 controls odd addresses.
Through the combination of A0, –CE1 and –CE2, both even and odd addresses can be accessed
with only the 8 bits of D0-D7.
Select signal for attribute memory.
The +WP signal will be asserted when the WP switch of this card is in the protect mode.
Thereafter, if the card configuration is set as an I/O card and 16-bit addressing is possible, the
IOIS16 signal is output from the card.
During an I/O read cycle, this signal is used as an acknowledge signal for the card.
This signal is asserted when the status of the +RDY/–BSY signal changes or when the WP switch
of this card changes.
This signal is asserted when it is necessary to delay completion of the memory-access.
The WAIT signal is not used with this card.
When this signal goes to a high level, reset is activated.
These signals are used to indicate the initial supply of voltage to this card.
VSENSE1 and VSENSE2 are NC (no connection) with this card.
A10–A0
(Input)
–CE1, –CE2
(Input)
–REG (Input)
+WP/–IOIS16
(Output)
–INPACK (Output)
–STSCHG
(Output)
–WAIT
(Output)
+RESET (Input)
VSENSE1,
VSENSE2
(Output)
Function
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