参数资料
型号: MTV10N100E
厂商: ON SEMICONDUCTOR
元件分类: JFETs
英文描述: 10 A, 1000 V, 1.3 ohm, N-CHANNEL, Si, POWER, MOSFET
封装: D3PAK-3
文件页数: 8/10页
文件大小: 269K
代理商: MTV10N100E
MTV10N100E
7
Motorola TMOS Power MOSFET Transistor Device Data
INFORMATION FOR USING THE DPAK SURFACE MOUNT PACKAGE
RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total
design. The footprint for the semiconductor packages must be
the correct size to ensure proper solder connection interface
between the board and the package. With the correct pad
geometry, the packages will self align when subjected to a
solder reflow process.
0.190
4.826
mm
inches
0.100
2.54
0.063
1.6
0.165
4.191
0.118
3.0
0.243
6.172
POWER DISSIPATION FOR A SURFACE MOUNT DEVICE
The power dissipation for a surface mount device is a
function of the drain pad size.
These can vary from the
minimum pad size for soldering to a pad size given for
maximum power dissipation. Power dissipation for a surface
mount device is determined by TJ(max), the maximum rated
junction temperature of the die, R
θJA, the thermal resistance
from the device junction to ambient, and the operating
temperature, TA. Using the values provided on the data sheet,
PD can be calculated as follows:
PD =
TJ(max) – TA
R
θJA
The values for the equation are found in the maximum
ratings table on the data sheet. Substituting these values into
the equation for an ambient temperature TA of 25°C, one can
calculate the power dissipation of the device. For a D3PAK
device, PD is calculated as follows.
PD =
150
°C – 25°C
62.5
°C/W
= 2.0 Watts
The 62.5
°C/W for the D3PAK package assumes the use of
the recommended footprint on a glass epoxy printed circuit
board to achieve a power dissipation of 2.0 Watts. There are
other alternatives to achieving higher power dissipation from
the surface mount packages. One is to increase the area of the
drain pad. By increasing the area of the drain pad, the power
dissipation can be increased. Although one can almost double
the power dissipation with this method, one will be giving up
area on the printed circuit board which can defeat the purpose
of using surface mount technology. For example, a graph of
R
θJA versus drain pad area is shown in Figure 15.
Figure 16. Thermal Resistance versus Drain Pad
Area for the D3PAK Package (Typical)
1.75 Watts
Board Material = 0.0625
G–10/FR–4, 2 oz Copper
80
100
60
40
20
10
8
6
4
2
0
3.0 Watts
5.0 Watts
TA = 25°C
A, AREA (SQUARE INCHES)
T
O
AMBIENT
(
C/W)°
R
JA
,THERMAL
RESIST
ANCE,
JUNCTION
θ
Another alternative would be to use a ceramic substrate or
an aluminum core board such as Thermal Clad
. Using a
board material such as Thermal Clad, an aluminum core
board, the power dissipation can be doubled using the same
footprint.
相关PDF资料
PDF描述
MTV10N100E-RL 10 A, 1000 V, 1.3 ohm, N-CHANNEL, Si, POWER, MOSFET
MTW6N100EG 6 A, 1000 V, 1.5 ohm, N-CHANNEL, Si, POWER, MOSFET, TO-247AE
MUN2112 100 mA, 50 V, PNP, Si, SMALL SIGNAL TRANSISTOR
MUN2214 100 mA, 50 V, NPN, Si, SMALL SIGNAL TRANSISTOR
MUN2212 100 mA, 50 V, NPN, Si, SMALL SIGNAL TRANSISTOR
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