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参数资料
| 型号： | MUAC4K64-90TDI |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 11/32页 |
| 文件大小： | 504K |
| 代理商： | MUAC4K64-90TDI |
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Control State Descriptions
MUAC Routing CoProcessor (RCP) Family
Rev. 4
19
Control State:
Read Comparand Register
Mnemonic:
RDs CR
Binary Op-Code: 0 XXX XXX 000 101
/W: HIGH
/AV: HIGH
PA:AA: n/c
Scope: S
Description: Reads bits 31–0 (DSC LOW) or 63-32 (DSC
HIGH) of the Comparand register to the DQ31–0 bus.
Control State:
Write Mask Register
Mnemonic:
WRs MRnnn
Binary Op-Code: XXX nnn 001 001
/W: LOW
/AV: HIGH
PA:AA: n/c
Scope: AS
Description: Writes data from the DQ31–0 bus to bits
31–0 (DSC LOW) or 63-32 (DSC HIGH) of Mask register
nnn. If nnn=000 then no data is written.
Control State:
Read Mask Register
Mnemonic:
RDs MRnnn
Binary Op-Code: XXX nnn 001 001
/W: HIGH
/AV: HIGH
PA:AA: n/c
Scope: S
Description: Reads bits 31–0 (DSC LOW) or 63-32 (DSC
HIGH) of Mask register nnn to the DQ31–0 bus. If
nnn=000 then the output is undefined.
MEMORY READ/WRITE
Control State:
Direct Write at Address
Mnemonic:
WRs[aaa]
Binary Op-Code: aaa
/W: LOW
/AV: LOW
PA:AA: aaa
Scope: AS
Description: Writes data from the DQ31-0 bus to bits
31-0 (DSC LOW) or 63-32 (DSC HIGH) of the location
defined by the address value present on the AC bus. The
write optionally can be masked by bits 31–0 (DSC LOW)
or 63-32 (DSC HIGH) of the mask register selected
through the Configuration register; when masking is
selected, only bits in the addressed location that
correspond to LOW values in the selected mask register
are updated. The validity of the location is set by the state
of the /VB input, /VB=LOW: Valid, /VB = HIGH: Empty.
This control state provides direct random access memory
writes. This control state, along with the Read cycle and
HIGH segment equivalents are the only ones that use
direct addressing. It is selected by the /AV line being
LOW. All other control states have the /AV line HIGH
whereby the AC bus carries a control code. This control
state is not available in software mode.
Control State:
Direct Read at Address
Mnemonic:
RDs[aaa]
Binary Op-Code: aaa
/W: HIGH
/AV: LOW
PA:AA: aaa
Scope: S
Description: Reads data from bits 31–0 (DSC LOW) or
63-32 (DSC HIGH) of the location defined by the address
value present on the AC bus to the DQ31–0 bus. This
control state provides direct random access memory reads.
This control state, along with the Write cycle and HIGH
segment equivalents are the only ones that use direct
addressing. It is selected by the /AV line being LOW. All
other control states have the /AV line HIGH whereby the
AC bus carries a control code. During the Read cycle, the
/VB line carries the Validity Bit value of the addressed
location. This control state is not available in software
mode.
Control State:
Indirect Write at Address
Mnemonic:
WRs[AR]{MRnnn}
Binary Op-Code: XXX nnn 000 000
/W: LOW
/AV: HIGH
PA:AA: aaa
Scope: AS
Description: Writes data from the DQ31-0 bus to bits
31-0 (DSC LOW) or 63-32 (DSC HIGH) of the location
defined by the contents of the Address register. The
validity of the location is set by the state of the /VB input,
/VB = LOW: Valid, /VB = HIGH: Empty. The write is
masked by bits 31–0 (DSC LOW) or 63-32 (DSC HIGH)
of the contents of Mask Register nnn. When nnn=000 no
mask is used; when masking is selected, only bits in the
addressed location that correspond to LOW values in the
selected mask register are updated. This control state
provides indirect random access memory writes.
Control State:
Indirect Read at Address
Mnemonic:
RDs[AR]
Binary Op-Code: XXX nnn 000 000
/W: HIGH
/AV: HIGH
PA:AA: aaa
Scope: S
Description: Reads data from bits 31–0 (DSC LOW) or
63-32 (DSC HIGH) of the location defined by the contents
of the Address register to the DQ31–0 bus. This control
state provides indirect random access memory reads.
During the Read cycle, the /VB line carries the Validity Bit
value of the addressed location.
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