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参数资料
| 型号： | MUAC4K64-90TDI |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 14/32页 |
| 文件大小： | 504K |
| 代理商： | MUAC4K64-90TDI |
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Control State Descriptions
MUAC Routing CoProcessor (RCP) Family
Rev. 4
21
Control State:
Write at Next Free Address
Mnemonic:
WRs[NFA]{MRnnn}
Binary Op-Code: XXX nnn 000 001
/W: LOW
/AV: HIGH
PA:AA: NFA
Scope: NFD
Description: Writes data from the DQ31-0 bus to bits
31-0 (DSC LOW) or 63-32 (DSC HIGH) of the next free
location in the Memory array. In a vertically cascaded
system, the write will take place in the device whose
/FI=LOW and /FF=HIGH, and at the highest-priority
location whose Validity bit is set HIGH. The validity of
the location is set by the state of the /VB input, /VB =
LOW: Valid, /VB = HIGH: Empty. The write is masked by
bits 31-0 (DSC LOW) or 63-32 (DSC HIGH) of the
contents of Mask Register nnn. When nnn=000 no mask is
used; when masking is selected, only bits in the addressed
location that correspond to LOW values in the selected
mask register are updated.
Control State:
Read Highest-Priority
Matching Location;
Increment Match Address
Mnemonic:
RDs[HPM]; NEXT
Binary Op-Code: XXX XXX 000 001
/W: HIGH
/AV: HIGH
PA:AA: HPMA
Scope: HPD
Description: Reads data from bits 31-0 (DSC LOW) or
63-32 (DSC HIGH) of the location defined by the
highest-priority matching location to the DQ31-0 bus. In
the event that the previous Comparison cycle resulted in a
mismatch, the DQ31-0 bus will remain in high-impedance.
The Next Highest-Priority Matching location is selected
and its address appears on the PA:AA bus lines.
DATA MOVE
Control State:
Move Data from Comparand
Register to Memory Indirect
Mnemonic:
MOV [AR],CR{MRnnn}
Binary Op-Code: XXX nnn 001 100
/W: LOW
/AV: HIGH
PA:AA: aaa
Scope: AS
Description: Moves data from the Comparand register to
the memory address defined by the contents of the
Address register. The validity of the location is set by the
state of the /VB input, /VB = LOW: Valid, /VB = HIGH:
Empty. The move is masked by the contents of Mask
Register nnn. When nnn=000 no mask is used; when
masking is selected, only bits in the addressed location
that correspond to LOW values in the selected mask
register are updated. DSC must be LOW.
Control State:
Move Data from Memory to
Comparand Register Indirect
Mnemonic:
MOV CR,[AR]{MRnnn}
Binary Op-Code: XXX nnn 001 100
/W: HIGH
/AV: HIGH
PA:AA: aaa
Scope: AS
Description: Moves data from the memory address
defined by the contents of the Address register to the
Comparand register. The move is masked by the contents
of Mask Register nnn. When nnn=000 no mask is used;
when masking is selected, only bits in the addressed
location that correspond to LOW values in the selected
mask register are updated. Note that the /VB line is not
driven during this operation. DSC must be LOW.
Control State:
Move Data from Comparand
Register to Next Free Address
Mnemonic:
MOV [NFA],CR{MRnnn}
Binary Op-Code: XXX nnn 001 101
/W: LOW
/AV: HIGH
PA:AA: NFA
Scope: NFD
Description: Moves data from the Comparand Register to
the Next Free address. In a vertically cascaded system, the
write will take place in the device whose /FI=LOW and
/FF=HIGH, and at the highest-priority location whose
Validity bit is set HIGH. The validity of the location is set
by the state of the /VB input, /VB = LOW: Valid, /VB =
HIGH: Empty. The move is masked by the contents of
Mask Register nnn. When nnn=000 no mask is used; when
masking is selected, only bits in the addressed location
that correspond to LOW values in the selected mask
register are updated. DSC must be LOW.
Control State:
Move Data from Comparand
Register to Highest-Priority
Matching Location
Mnemonic:
MOV [HPM],CR{MRnnn}
Binary Op-Code: XXX nnn 001 110
/W: LOW
/AV: HIGH
PA:AA: HPMA
Scope: HPD
Description: Moves data from the Comparand register to
the Highest-Priority Matching address from the previous
Comparison cycle. The validity of the location is set by the
state of the /VB input, /VB = LOW: Valid, /VB = HIGH:
Empty. The move is masked by the contents of Mask
Register nnn. When nnn=000 no mask is used; when
masking is selected, only bits in the addressed location
that correspond to LOW values in the selected mask
register are updated. DSC must be LOW.
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