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参数资料
| 型号： | MUAC4K64-90TDI |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP100 |
| 封装： | TQFP-100 |
| 文件页数： | 15/32页 |
| 文件大小： | 504K |
| 代理商： | MUAC4K64-90TDI |
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MUAC Routing CoProcessor (RCP) Family
Control State Descriptions
22
Rev. 4
Control State:
Move Data from Highest-Priority
Matching Location to Comparand
Register
Mnemonic:
MOV CR,[HPM]{MRnnn}
Binary Op-Code: XXX nnn 001 110
/W: HIGH
/AV: HIGH
PA:AA: HPMA
Scope: HPD
Description: Moves data from the Highest-Priority Match
address from the previous Comparison cycle to the
Comparand register. The move is masked by the contents
of Mask Register nnn. When nnn=000 no mask is used;
when masking is selected, only bits in the addressed
location that correspond to LOW values in the selected
mask register are updated. Note that the /VB line is not
driven during this operation. DSC must be LOW.
COMPARISON
Control State:
Compare Comparand Register
with Memory Array
Mnemonic:
CMP CR,{MRnnn}
Binary Op-Code: XXX nnn 011 000
/W: LOW
/AV: HIGH
PA:AA: HPMA
Scope: AS
Description: The Comparand register is compared with
all locations in the Memory array that have their Validity
bits set LOW. The comparison is masked by the contents
of Mask Register nnn. When nnn=000 no mask is used;
when masking is selected, only bits that correspond to
LOW values in the selected mask register are compared.
DSC must be LOW.
Control State:
Compare Data Bus with Memory
Array
Mnemonic:
CMPs DQ,{MRnnn}
Binary Op-Code: XXX nnn 011 001
/W: LOW
/AV: HIGH
PA:AA: HPMA
Scope: AS
Description: A comparand is formed such that bits 63-32
(DSC LOW) or 31-0 (DSC HIGH) of the Comparand
register provide bits 63-32 (DSC LOW) or 31-0 (DSC
HIGH) of the comparand, and bits 31-0 of the DQ bus
provide bits 31-0 (DSC LOW) or 63-32 (DSC HIGH) of
the comparand. This comparand is compared with all
locations in the Memory array that have their Validity bits
set LOW. The comparison is masked by the contents of
Mask Register nnn. When nnn=000 no mask is used; when
masking is selected, only bits that correspond to LOW
values in the selected mask register are compared.
Control State:
Compare Data Bus with Memory
Array; Write Data Bus to
Comparand Register
Mnemonic:
CMPWs DQ,{MRnnn}
Binary Op-Code: XXX nnn 011 010
/W: LOW
/AV: HIGH
PA:AA: HPMA
Scope: AS
Description: The data from the DQ31–0 bus is written to
bits 31–0 (DSC LOW) or 63–32 (DSC HIGH) of the
Comparand register. The data from the 64 bit Comparand
register then is compared with all locations in the Memory
array that have their Validity bits set LOW. The
comparison is masked by the contents of Mask Register
nnn. When nnn=000 no mask is used. Note that the
selected mask register masks the comparison and not the
write to Comparand register.
Control State:
Compare Data Bus with Memory
Array (Ternary Mode)
Mnemonic:
CMPT DQ
Binary Op-Code: XXX nnn 011 100
/W: LOW
/AV: HIGH
PA:AA: HPMA
Scope: AS
Description: The data from the DQ bus is used as both
bits 31–0 of the comparand and a mask. The bit-wise
complement of the data from the DQ bus is used as both
bits 63–32 of the comparand and a mask. The resulting
64–bit comparand and mask are compared with all
locations in the Memory array that have their Validity bits
set LOW. The CMPT DQ instruction overwrites neither
the comparand nor any mask register. DSC must be LOW.
Control State:
Advance to Next Matching
Location
Mnemonic:
NEXT
Binary Op-Code: XXX nnn 011 011
/W: LOW
/AV: HIGH
PA:AA: HPMA
Scope: HPD
Description: Advances the Match address to the next
matching location when the previous Comparison cycle
resulted in a multiple match. The /MF flag will go HIGH
when all matches have been exhausted, therefore the
scheme operates in vertically cascaded systems through
the priority daisy chain. DSC must be LOW.
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