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参数资料
| 型号： | MUPA64K16-15TJI |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQFP128 |
| 封装： | LQFP-128 |
| 文件页数： | 15/19页 |
| 文件大小： | 380K |
| 代理商： | MUPA64K16-15TJI |
MUPA64K16 Alto Priority Queue Scheduler
MUSIC Semiconductors Confidential
5
Rev 0.3 Draft
Table 2: Registers
Register
Description
R/W
Size
Reg[2:0]
/W
Input Data Register
(IDR)
Contains the associated data value
for the next INSERT or BOTH
instruction
W
16
1
0
Input Key Register
(IKR)
Contains the key value for the next
INSERT or BOTH instruction
W
32
0
Minimum Data
Register
(MDR)
Contains the data associated with the
minimum key value returned by a
PEEK, EXTRACT or BOTH
instruction
R
16
1
Minimum Key Register
(MKR)
Contains the minimum key value
returned by the PEEK, EXTRACT or
BOTH instruction
R
32
0
1
Size Registers (16)
(SR)
Indicates the size of each of the
priority queues
R/W
17
2
0/1
Wrap Registers (16)
(WR)
Holds the value that is to be
considered minimum
R/W
32
3
0/1
UID Get Registers (16)
(UGR)
Holds the next available unique
identifier that is not in use
R
17
5
1
UID Put Register
(UPR)
Accepts identifiers that are no longer
in use to be returned to the free list
W
16
5
0
Mode Register (MR)
Determines the number of
independent priority queues in use: 1,
2 4, 8 or 16
R/W
3
4
0/1
Status Register (STR)
Provides device status
R
21
6
1
Reserved
R/W
N/A
7
0/1
ADS
PQ[3:0]
MUX
UID Put
Register
Size
Register x16
Status
Register
Input Data
Register
Input Key
Register
MUX
DQ[31:0]
REG[2:0]
Wrap
Register x16
Mode
Register
Min Data
Register
Min Key
Register
UID Get
Register x16
MUX
STR[4:0]
MUX
AD[15:0]
Figure 3: Register Datapath
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