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参数资料
| 型号： | MX10EXAQI |
| 厂商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16-BIT, FLASH, 30 MHz, MICROCONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 26/55页 |
| 文件大小： | 476K |
| 代理商： | MX10EXAQI |
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P/N:PM0625 Specifications subject to change without notice, contact your sales representatives for the most update information. REV. 1.0, JUL. 01, 2005
MX10EXA
When the watchdog underflows, the following action takes
place (see Figure 14):
Autoload takes place.
Watchdog time-out flag is set
Watchdog run bit unchanged.
Autoload (WDL) register unchanged.
Prescaler tap unchanged.
All other device action same as external reset.
Note that if the watchdog underflows, the program counter
will be loaded from the reset vector as in the case of an
internal reset. The watchdog time-out flag can be exam-
ined to determine if the watchdog has caused the reset
condition. The watchdog time-out flag bit can be cleared
by software.
WDCON Register Bit Definitions
WDCON.7
PRE2
Prescaler Select 2, reset to 1
WDCON.6
PREl
Prescaler Select 1, reset to 1
WDCON.5
PRE0
Prescaler Select 0, reset to 1
WDCON.4
-
WDCON.3
-
WDCON.2
WDRUN
Watchdog Run Control bit, re
set to 1
WDCON.1
WDTOF
Time out flag
WDCON.0
-
UARTs
Baud rate selection is somewhat different due to the
clocking scheme used for the XA timers.
Some other enhancements have been made to UART
operation. The first is that there are separate interrupt
vectors for each UART’s transmit and receive functions.
The UART transmitter has been double buffered, allow-
ing packed transmission of data with no gaps between
bytes and less critical interrupt service routine timing. A
break detect function has been added to the UART. This
operates independently of the UART itself and provides
a start-of-break status bit that the program may test.
Finally, an Overrun Error flag has been added to detect
missed characters in the received data stream. The
double buffered UART transmitter may require some
software changes in code written for the original XA single
buffered UART.
Each UART baud rate is determined by either a fixed
division of the oscillator (in UART modes 0 and 2) or by
the timer 1 or timer 2 overflow rate (in UART modes 1
and 3).
Timer 1 defaults to clock both UART0 and UART1. Timer
2 can be programmed to clock either UART0 through
T2CON (via bits R0CLK and T0CLK) or UART1 through
T2MOD (via bits R1CLK and T1 CLK). In this case, the
UART not clocked by T2 could use T1 as the clock source.
The serial port receive and transmit registers are both
accessed at Special Function Register SnBUF Writing
to SnBUF loads the transmit register, and reading SnBUF
accesses a physically separate receive register.
The serial port can operate in 4 modes:
Mode 0: Serial I/O expansion mode. Serial data enters
and exits through RxDn. TxDn outputs the shift clock. 8
bits are transmitted/received (LSB first). (The baud rate
is fixed at 1/16 the oscillator frequency.)
Mode 1: Standard 8-bit UART mode. 10 bits are
transmitted(through TxDn) or received (through RxDn): a
start bit (0), 8 data bits (LSB first), and a stop bit (1). On
receive, the stop bit goes intoRB8 in Special Function
Register SnCON. The baud rate is variable.
Mode 2: Fixed rate 9-bit UART mode. 11 bits are trans-
mitted (through TxD) or received (through RxD): start bit
(0), 8 data bits (LSB first), a programmable 9th data bit,
and a stop bit (1). On Transmit, the 9th data bit TB8_n in
SnCON) can be assigned the value of 0 or 1. Or, for
example, the parity bit (P, in the PSW) could be moved
into TB8_n. On receive, the 9th data bit goes into RB8_n
in Special Function Register SnCON, while the stop bit
is ignored. The baud rate is programmable to 1/32 of the
oscillator frequency.
Mode 3: Standard 9-bit UART mode. 11 bits are trans-
mitted (through TxDn) or received (through RxDn): a start
bit (0), 8 data bits (LSB first), a programmable 9th data
bit, and a stop bit (1). In fact, Mode 3 is the same as
Mode 2 in all respects except baud rate. The baud rate in
Mode 3 is variable.
In all four modes, transmission is initiated by any in-
struction that uses SnBUF as a destination register. Re-
ception is initiated in Mode 0 by the condition RI_n = 0
and REN_n = 1. Reception is initiated in the other modes
by the incoming start bit if REN_n = 1.
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