参数资料
| 型号： | MX7705EUE+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 22/33页 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 2CH 16-TSSOP |
| 产品培训模块： | MAX11200 ADC Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 96 |
| 位数： | 16 |
| 采样率（每秒）： | 500 |
| 数据接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 755mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
| 输入数目和类型： | 2 个差分，单极 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页当前第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页
Next, an internally generated voltage (VREF / GAIN) is
applied across AIN+ and AIN-. This condition results in
the full-scale calibration.
Start self-calibration by setting MD1 = 0, MD0 = 1, and
FSYNC = 0 in the setup register. Self-calibration com-
pletes in 6 x 1/output data rate. The MD1 and MD0 bits
both return to zero at the end of calibration. The device
returns to normal acquisition mode and performs a con-
version, which completes in 3 x 1/output data rate after
the self-calibration sequence.
The DRDY output goes high at the start of calibration
and falls low when the calibration is complete and the
next conversion result is valid in the data register. The
total time for self-calibration and one conversion (time
until DRDY goes low) is 9 x 1/output data rate. If DRDY
is low before or goes low during the calibration com-
mand write to the setup register, DRDY takes up to one
additional modulator cycle (128/fCLKIN) to return high to
indicate a calibration or conversion in progress.
System Calibration
System calibration compensates for offset and gain
errors for the entire analog signal path including the
ADC, signal conditioning, and signal source. System
calibration is a two-step process and requires individ-
ual zero-scale and full-scale calibrations on the select-
ed channel at a specified PGA gain. Recalibration is
recommended with changes in ambient temperature,
supply voltage, bipolar/unipolar mode, PGA gain, and
output data rate. Before starting calibration, set the
PGA gain and the desired channel.
Set the zero-scale reference point across AIN+ and AIN-.
Start the zero-scale calibration by setting MD1 = 1, MD0
= 0, and FSYNC = 0 in the setup register. When zero-
scale calibration is complete (3 x 1/output data rate),
MD1 and MD0 both return to zero. DRDY goes high at the
start of the zero-scale system calibration and returns low
when there is a valid word in the data register (4 x 1/out-
put data rate). The time until DRDY goes low is com-
prised of one zero-scale calibration sequence (3 x
1/output data rate) and one conversion on the AIN volt-
age (1 x 1/output data rate). If DRDY is low before or
goes low during the calibration command write to the
setup register, DRDY takes up to one additional modula-
tor cycle (128/fCLKIN) to return high to indicate a calibra-
tion or conversion in progress.
After performing a zero-scale calibration, connect the
analog inputs to the full-scale voltage level (VREF /
GAIN). Perform a full-scale calibration by setting MD1 =
1 and MD0 = 1. After 3 x 1/output data rate, MD1 and
MD0 both return to zero at the completion of full-scale
calibration. DRDY goes high at the beginning of cali-
bration and returns low after calibration is complete
and new data is in the data register (4 x 1/output data
rate). The time until DRDY goes low is comprised of
one full-scale calibration sequence (3 x 1/output data
rate) and one conversion on the AIN voltage (1 x 1/out-
put data rate). If DRDY is low before or goes low during
the calibration-command write to the setup register,
DRDY takes up to one additional modulator cycle
(128/fCLKIN) to return high to indicate a calibration or
conversion in progress.
In bipolar mode, the midpoint (zero scale) and positive
full scale of the transfer function are used to calculate the
calibration coefficients of the gain and offset registers. In
unipolar mode, system calibration is performed using the
two endpoints of the transfer function (Figures 4 and 5).
Power-Down Modes
The MX7705 includes a power-down mode to save
power. Select power-down mode by setting PD = 1 in
the communications register. The PD bit does not affect
the serial interface or the status of the DRDY line. While
in power-down mode, the MX7705 retains the contents
of all of its registers. Placing the part in power-down
mode reduces current consumption to 2A (typ) when
in external clock mode and with CLKIN connected to
VDD or GND. If DRDY is high before the part enters
power-down mode, then DRDY remains high until the
part returns to normal operation mode and new data is
available in the data register. If DRDY is low before the
part enters power-down mode, indicating new data in
the data register, the data register can be read during
power-down mode. DRDY goes high at the end of this
read operation. If the new data remains unread, DRDY
stays low until the MX7705 is taken out of power-down
mode and resumes data conversion. Resume normal
operation by setting PD = 0. The device begins a new
conversion with a result appearing in 3 x 1/output data
rate + tP, where tP = 2000 x 1/fCLKIN, after PD is set to
0. If the clock is stopped during power-down mode,
allow sufficient time for the clock to start up before
resuming conversion.
If CLKDIS = 0, CLKOUT remains active during power-
down mode to provide a clock source for other devices
in the system.
MX7705
16-Bit, Low-Power, 2-Channel,
Sigma-Delta ADC
______________________________________________________________________________________
29
相关PDF资料 |
PDF描述 |
|---|---|
| VI-B6Z-IU-F3 | CONVERTER MOD DC/DC 2V 80W |
| VI-B6Z-IU-F2 | CONVERTER MOD DC/DC 2V 80W |
| MAX1185ECM/V+ | IC ADC 10BIT 20MSPS DL LP 48TQFP |
| MS27497T16F99PB | CONN RCPT 23POS WALL MNT W/PINS |
| IDT723644L12PF8 | IC FIFO SYNC 2048X36 128QFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MX7705EUE+ | 功能描述:模数转换器 - ADC 16-Bit 2Ch Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MX7705EUE+T | 功能描述:模数转换器 - ADC 16-Bit 2Ch Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MX7705EUE-T | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MX7705EWE | 功能描述:模数转换器 - ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
| MX7705EWE+ | 功能描述:模数转换器 - ADC 16-Bit 2Ch Precision ADC RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
发布紧急采购，3分钟左右您将得到回复。