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参数资料
| 型号： | MX98216EC |
| 厂商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封装： | PLASTIC, QFP-208 |
| 文件页数： | 13/37页 |
| 文件大小： | 269K |
| 代理商： | MX98216EC |
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MX98216EC
P/N:PM0781
REV. 0.2, Apr, 18, 2001
20
LED Control and VLAN Group Reset (Reg27H), default = 0x0200H
BIT
DESCRIPTION
TYPE
DEFAULT
27.0
Port Grouping Command
When, initially, the execution of default values of the VLAN registers
(Reg00H-17H) or VLAN grouping settings required via CPU/EEPROM,
VLAN grouping contents need to write into the registers; then, grouping
command is put into action.
After grouping command is done, the bit will
be self-clean to 0.
0 : Idle
1 : Port regrouping enable
R/W
0
27.2-1
Reserved
R/W
00
27.3
Broadcast Storm LED
0 : LED displays the broadcast storm symptom in high priority packets
1 : LED displays the broadcast storm symptom of all packets
R/W
1
27.4
Packet Loss LED
0 : LED displays the high priority packet loss
1 : LED displays all packet loss
R/W
1
27.15-5
N/A
0x010H
CPU Access Data (Reg28H), default = 0x0000H
BIT
DESCRIPTION
TYPE
DEFAULT
28.15-0
Access Data
Generally, bit 15-0 is the access data for PHY registers and address table.
In case, CPU requires to select PHY ID and register number before PHY
register access.
The starting PHY ID for the switch is 0.
Bit 4-0 can be
presented for PHY register number and bit 9-5 for PHY ID in address
selection of PHY registers operation.
R/W
0x0000H
PHY/Address Table Operation Command (Reg29H), default = 0x0000H
BIT
DESCRIPTION
TYPE
DEFAULT
29.0
CPU Action
If CPU takes read/write actions to address table or PHY registers, set the
bit on.
After action done, the bit will be self-clean to 0.
0 : Idle
1 : CPU action
R/W
0
29.1
CPU Read/Write
Read or write action set to address table or PHY registers.
0 : Read operation
1 : Write operation
R/W
0
29.2
PHY/ALR Selection
CPU access to PHY or address table
0 : PHY access
1 : Address table access
R/W
0
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