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参数资料
| 型号： | MX98216EC |
| 厂商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封装： | PLASTIC, QFP-208 |
| 文件页数： | 20/37页 |
| 文件大小： | 269K |
| 代理商： | MX98216EC |
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MX98216EC
P/N:PM0781
REV. 0.2, Apr, 18, 2001
27
their network activity or fundamental network broadcasting will not affect or get distributed across those VLAN groups
to each other.
In this way, it can reduce the need for unwanted traffic in the network.
Moreover, the
damaged/abnormal ports can be isolated by removing them from VLAN groups' list, so as to prevent network
meltdown.
Port-based VLAN in MX98216EC is also very flexible that every port can be shared by multiple groups as
the "trunk port" while the other unshared ports are remained independent.
Queue Management
MX98216EC utilizes the store-and-forward switching scheme, which needs memory for frame reception and
transmission buffering.
In MX98216EC, the embedded buffer memory is partitioned into pages which dynamically
allocates the related frame data and switching information.
The buffer management control unit dispatches pointers
pointing to those pages upon frames reception of the egress ports.
For unicast frames, the occupied buffer pages are released after the corresponding ports complete transmission.
Their pointers are returned to buffer management control unit for reuse.
For broadcast frames, the switch controller
count the times of transmission of the same broadcast frame till all ports finish the broadcast transmission, then the
occupied memory space are released to the free buffer pool.
Since there are various kinds of page/pointer requests for the buffer management, a queue manager is used in
MX98216EC to handle those access requests.
Via a proprietary arbitration method, the queue manager grants fair
enough throughput for each port to transmit at wire speed.
93C46 EEPROM Interface
Provide serial interface to load the values of external EEPROM which switch can configure in advance.
At initial
stage, switch will loads the data to internal registers and operates as expected.
Either EEPROM or CPU interface
can be used once a time.
CPU Interface
MX98216EC provides another powerful way to configure the value of register via CPU, which can access its as well as
PHY registers and the address table at any time.
Basically, MAC address look up, content of address table status
and frozen a dedicated address are the major function for CPU access through address table.
Following is the basic
system diagram for the connection of host processor, switch, and PHY.
Host
Processor
MX98216EC
Switch
Octal PHY
OUTCLK
INCLK
IODATA
MDC
MDIO
Serial Management Block Diagram via Switch and PHY
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