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参数资料
| 型号： | MX98216EC |
| 厂商： | MACRONIX INTERNATIONAL CO LTD |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 16 CHANNEL(S), 100M bps, LOCAL AREA NETWORK CONTROLLER, PQFP208 |
| 封装： | PLASTIC, QFP-208 |
| 文件页数： | 18/37页 |
| 文件大小： | 269K |
| 代理商： | MX98216EC |
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MX98216EC
P/N:PM0781
REV. 0.2, Apr, 18, 2001
25
PHY Management
The PHY determines the operation mode of each port, which are classified as 10Mbps-half duplex, 10Mbps-full duplex,
100Mbps-half duplex, 100Mbps-full duplex.
The MAC of each port is connected to the PHY through RMII interface.
The PHY starting ID mapped to the switch is zero.
The switch supports PHY management through the serial
MDC/MDIO interface.
The switch will continuously read the registers of each PHY based on PHY ID to get the latest
information such as link status, speed, operation mode of each port while it is in auto-negotiation.
When a port of the
switch forced at fixed operation mode, it will not listen any response from the PHY through MDC/MDIO so that
consistent speed and duplex in PHY as well as switch is required in force operation mode.
Frame Reception
The frame received on 2-bit wide receive channel of RMII interface is queued in receive FIFO, and then stored into
embedded buffer memory.
Several error conditions will be identified during data reception.
1.Runt frame error, if the frame size is less than 64 bytes;
2.CRC error, if FCS is not matched to the result of CRC calculation;
3.Long frame error, if frame size is larger than 1536 bytes;
4.Alignment error, if frame length is of non-integral number of octets;
The above frames will be discarded.
If no errors have been detected, the frame is stored and forwarded to egress
port at wire speed.
Several pages of buffer memory could be occupied for frame storage, on each page free memory
is allocated.
The data link management frames, namely IEEE 802.3x "pause" frame is recognized and no frame
storage occurs.
Frame Transmission
Frame transmission begins while the output queue of physical port is not empty.
The frame data is moved to output
FIFO from embedded buffer memory, and converted to 2-bit stream through transmit channel of RMII interface.
MX98216EC transmits frames in accordance to IEEE 802.3 standard.
The egress port is responsible for preamble
insertion, collision back-off, and inter packet gap keeping.
While late collision happens on half-duplex port, the
transmitted frame is aborted.
If a packet has continuously met 16-time collisions, it will be dropped and the packet
will be recovered by upper protocol.
In full-duplex mode, the egress port ignores the signaling of carrier activity and
collision detection on channel media.
Broadcast Storm Control
Three types of frames are viewed as broadcast frames in MX98216EC:
1. Received frame with DL_DA as FF-FF-FF-FF-FF-FF
2. Received frame with DL_DA as 1?-??-??-??-??-??
3. Received frame with unknown destination (unicast or multicast) address
To prevent network melted down, a state of complete network overload, due to broadcast storm (incorrect packet
broadcast on a network that cause almost all hosts respond at once and hence storming the network with broadcast
packets), users can program to restrict the storage amount of broadcast frames in MX98216EC.
While the storage of
broadcast frame goes over the threshold, the next coming broadcast frame(s) is dropped.
Flow Control
Flow control is implemented to avoid abnormal packet drop due to traffic congestion on egress ports.
Basically,
alternative back-pressure mechanism uses jam packet in half-duplex and 802.3x pause frame does in full-duplex
mode.
Flow control is active or inactive based on the internal per port and global reception thresholds in buffer.
The switch implements standard 802.3x flow control whose frame is defined as follow.
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