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参数资料
| 型号： | NAND01GW3A2AN1 |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 128M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| 封装： | 12 X 20 MM, PLASTIC, TSOP-48 |
| 文件页数： | 21/57页 |
| 文件大小： | 916K |
| 代理商： | NAND01GW3A2AN1 |
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NAND128-A, NAND256-A, NAND512-A, NAND01G-A
28/57
Read Status Register
The device contains a Status Register which pro-
vides information on the current or previous Pro-
gram or Erase operation. The various bits in the
Status Register convey information and errors on
the operation.
The Status Register is read by issuing the Read
Status Register command. The Status Register in-
formation is present on the output data bus (I/O0-
I/O7) on the falling edge of Chip Enable or Read
Enable, whichever occurs last. When several
memories are connected in a system, the use of
Chip Enable and Read Enable signals allows the
system to poll each device separately, even when
the Ready/Busy pins are common-wired. It is not
necessary to toggle the Chip Enable or Read En-
able signals to update the contents of the Status
Register.
After the Read Status Register command has
been issued, the device remains in Read Status
Register mode until another command is issued.
Therefore if a Read Status Register command is
issued during a Random Read cycle a new read
command must be issued to continue with a Page
Read or Sequential Row Read operation.
The Status Register bits are summarized in Table
11., Status Register Bits. Refer to Table 11. in
conjunction with the following text descriptions.
Write Protection Bit (SR7). The Write Protection
bit can be used to identify if the device is protected
or not. If the Write Protection bit is set to ‘1’ the de-
vice is not protected and program or erase opera-
tions are allowed. If the Write Protection bit is set
to ‘0’ the device is protected and program or erase
operations are not allowed.
P/E/R Controller Bit (SR6). The Program/Erase/
Read Controller bit indicates whether the P/E/R
Controller is active or inactive. When the P/E/R
Controller bit is set to ‘0’, the P/E/R Controller is
active (device is busy); when the bit is set to ‘1’, the
P/E/R Controller is inactive (device is ready).
Error Bit (SR0). The Error bit is used to identify if
any errors have been detected by the P/E/R Con-
troller. The Error Bit is set to ’1’ when a program or
erase operation has failed to write the correct data
to the memory. If the Error Bit is set to ‘0’ the oper-
ation has completed successfully.
SR5, SR4, SR3, SR2 and SR1 are Reserved.
相关PDF资料 |
PDF描述 |
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| NAND01GW3A2AZB1E | 128M X 8 FLASH 3V PROM, 35 ns, PBGA63 |
| NAND01GW3A0CZB1 | 128M X 8 FLASH 3V PROM, 35 ns, PBGA63 |
| NAND01GW3A2BN6T | 128M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND01GW3A2CN6T | 128M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
| NAND01GW3A2AN1F | 128M X 8 FLASH 3V PROM, 35 ns, PDSO48 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| NAND01GW3A2AN1E | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND01GW3A2AN1F | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND01GW3A2AN1T | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND01GW3A2AN6 | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories |
| NAND01GW3A2AN6E | 功能描述:IC FLASH 1GBIT 48TSOP RoHS:是 类别:集成电路 (IC) >> 存储器 系列:- 标准包装:576 系列:- 格式 - 存储器:闪存 存储器类型:闪存 - NAND 存储容量:512M（64M x 8） 速度:- 接口:并联 电源电压:2.7 V ~ 3.6 V 工作温度:-40°C ~ 85°C 封装/外壳:48-TFSOP（0.724"，18.40mm 宽） 供应商设备封装:48-TSOP 包装:托盘 其它名称:497-5040 |
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