参数资料
| 型号： | NB4N121KMNR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 1/9页 |
| 文件大小： | 0K |
| 描述： | IC CLK BUFFER 1:21 400MHZ 52-QFN |
| 标准包装： | 2,000 |
| 类型： | 扇出缓冲器（分配） |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:21 |
| 差分 - 输入:输出： | 是/是 |
| 输入： | CML，LVCMOS，LVDS，LVPECL，LVTTL |
| 输出： | HCSL |
| 频率 - 最大： | 400MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 52-VFQFN 裸露焊盘 |
| 供应商设备封装： | 52-QFN（8x8） |
| 包装： | 带卷 (TR) |
Semiconductor Components Industries, LLC, 2012
April, 2012 Rev. 6
1
Publication Order Number:
NB4N121K/D
NB4N121K
3.3V Differential 1:21
Differential Fanout Clock
Driver with HCSL level
Output
Description
The NB4N121K is a Clock differential input fanout distribution 1 to
21 HCSL level differential outputs, optimized for ultra low
propagation delay variation. The NB4N121K is designed with HCSL
clock distribution for FBDIMM applications in mind.
Inputs can accept differential LVPECL, CML, or LVDS levels.
Singleended LVPECL, CML, LVCMOS or LVTTL levels are
and 13). Clock input pins incorporate an internal 50
W on die
termination resistors.
Output drive current at IREF (Pin 1) for 1X load is selected by
connecting to GND. To drive a 2X load, connect IREF to VCC. See
Figure 9.
The NB4N121K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB4N121K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
400 MHz
340 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
Dtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
Additive Phase RMS Jitter: 1 ps Max
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
Differential HCSL Output Level (700 mV PeaktoPeak)
PbFree Packages are Available
A
= Assembly Site
WL
= Wafer Lot
YY
= Year
WW
= Work Week
G
= PbFree Package
*For additional marking information, refer to
Application Note AND8002/D.
QFN52
MN SUFFIX
CASE 485M
MARKING DIAGRAM*
http://onsemi.com
NB4N
121K
AWLYYWWG
1
52
Figure 1. Pin Configuration (Top View)
Q0
Q1
Q19
Q20
CLK
VCC
GND
RREF
IREF
See detailed ordering and shipping information in the
package dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
VTCLK
152
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