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参数资料
| 型号： | NCL30100ADLMGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 8/27页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO MR16 FORMFACTOR |
| 设计资源： | NCL30100ADLMGEVB Schematic NCL30100ADLMGEVB Gerber Files NCL30100ADLMGEVB Bill of Materials |
| 标准包装： | 1 |
| 输出及类型： | 1，非隔离 |
| 输入电压： | 12V |
| 已供物品： | 板 |
| 已用 IC / 零件： | NCL30100 |
| 其它名称： | NCL30100ADLMGEVBOS |
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NCL30100
Once the external MOSFET is switched on, the inductor
current starts to flow through the sense resistor R CS . The
current creates a voltage drop V CS on the resistor R CS , which
is negative with respect to GND. Since the comparator
connected to CS pin requires a positive voltage, a voltage
From Input Voltage
Compensation Block
VOffset
V shift is developed across the resistor R shift by a current
source which level ? shifts the negative voltage V CS . The
level ? shift current is in the range from 12.5 to 50 m A
depending on the optional input voltage compensation loop
control block signal (see more details in the input voltage
compensation section). The peak inductor current is equal
to:
CT
CT
50 m A
VOffset to VDD
To Latch’s Set Input
To Latch’s Output
I pk +
I CS @ R shift * V th
R CS
(eq. 1)
To achieve the best I pk precision, higher values of I CS
should be used. The Equation 1 shows the higher drop on
R CS reduces the influence of the V th tolerance. Vth is the
comparator threshold which is nominally 38 mV.
A typical CS pin voltage waveform for continuous
condition mode is shown in Figure 16.
GND
Figure 17. OFF Time Control
During the switch ? on time, the C T capacitor is kept
discharged by an internal switch. As soon as the latch output
V
I shift = 50 m A
I shift = 12.5 m A
changes to a low state, the I source is enabled and the voltage
across C T starts to ramp ? up until its value reaches the
threshold given by the V offset . The current injected into IVC
can change this threshold. The IVC operation will be
discussed in the next section.
V
VDD
0
Switch
t
CT pin
Voltage
I VC Goes Up
I VC Goes Down
Turn on
Voffset
Figure 16. CS Pin Voltage
I1
I2
I3
0
Figure 16 also shows the effect of the inductor current
t off ? min
t
based on the range of control possible via the IVC input.
OFF Time Control
The internal current source, together with an external
capacitor, controls the switch ? off time. In addition, the
optional IVC control signal can modulate the off time based
on input line voltage conditions. This block is illustrated in
Figure 17.
Figure 18. CT Pin Voltage
The voltage that can be observed on C T pin is shown in
Figure 18. The bold line shows the minimum IVC current
when the off time is at its minimum. The amount of current
injected into the IVC input can increase the off time by
changing the turn off comparator switching threshold. I1, I2,
http://onsemi.com
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