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参数资料
| 型号： | NCL30100ADLMGEVB |
| 厂商： | ON Semiconductor |
| 文件页数： | 9/27页 |
| 文件大小： | 0K |
| 描述： | BOARD DEMO MR16 FORMFACTOR |
| 设计资源： | NCL30100ADLMGEVB Schematic NCL30100ADLMGEVB Gerber Files NCL30100ADLMGEVB Bill of Materials |
| 标准包装： | 1 |
| 输出及类型： | 1，非隔离 |
| 输入电压： | 12V |
| 已供物品： | 板 |
| 已用 IC / 零件： | NCL30100 |
| 其它名称： | NCL30100ADLMGEVBOS |
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NCL30100
and I3 represent different delays depending on the
magnitude of IVC.
V CC
Gate Driver
The Gate Driver consists of a CMOS buffer designed to
directly drive a power MOSFET. It features unbalanced
source and sink capabilities to optimize switch on and off
performance without additional external components. The
power MOSFET is switched off at high drain current, to
minimize its switch off losses the sink capability of the gate
driver is increased for a faster switch off. On the other hand,
the source capability of the driver is reduced to slow ? down
IVC
17 k W
Current
Mirror
1:1
Current
Mirror
1:1
V Offset
25 k W
To OFF
Time
Comparator
the power MOSFET at switch on in order to reduce EMI
generation. Whenever the IC supply voltage is lower than
the under voltage threshold, the Gate Driver is low, pulling
m A
IVC Pin Sink Current
down the gate to ground thus eliminating the need for an
external resistor.
Input Voltage Compensation:
The Input Voltage Compensation block gives the user
optional flexibility to sense the input voltage and modify the
current sense threshold and off time. This function provides
a feed forward mechanism that can be used when the input
voltage of the controller is loosely regulated to improve
output current regulation. If the input voltage is well
regulated, the IVC input can also be used to adjust the offset
of the off time comparator and the current sense control to
achieve the best current regulation accuracy.
An external resistor connected between IVC and the input
supply results in a current being injected into this pin which
has an internal 17 k W resistor connected to a current mirror.
This current information is used to modify V offset and I CS .
By changing V offset the off time comparator threshold is
modified and the off time is increased. A small capacitor
should be connected between the IVC pin and ground to
filter out noise generated during switching period. Figure 19
shows the simplified internal schematic:
Figure 19. Input Voltage Compensation, OFF Time
Control
V
V DD
V offset
0
Figure 20. IVC Loop Transfer Characteristic
The transfer characteristic (output voltage to input
current) of the input voltage compensation loop control
block can be seen in Figure 20. V DD refers to the internal
stabilized supply. If no IVC current is injected, the off time
comparator is set to V offset .
The value of the current injected into IVC also change Ics.
This is accomplished by changing the voltage drop on R shift .
The corresponding block diagram of the IVC pin can be seen
in Figure 21.
To Current Sense Comparator
17 k W
IVC
Current
CS
Mirror
4:3
37.5 m A
12.5 m A
Figure 21. Input Voltage Compensation Loop – Current Sense Control
http://onsemi.com
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