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| 型号： | NCP1030DMR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 15/19页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM OTP OVD HV MICRO8 |
| 标准包装： | 1 |
| 输出隔离： | 任意一种 |
| 频率范围： | 260kHz ~ 325kHz |
| 输入电压： | 7.6 V ~ 16 V |
| 输出电压： | 200V |
| 功率（瓦特）： | 582mW |
| 工作温度： | -40°C ~ 150°C |
| 封装/外壳： | 8-TSSOP，8-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | Micro8? |
| 包装： | 剪切带 (CT) |
| 其它名称： | NCP1030DMR2GOSCT |
NCP1030, NCP1031
PWM Comparator and Latch
The Pulse Width Modulator (PWM) Comparator
compares the error amplifier output (COMP) to the C T
Ramp and generates a proportional duty cycle. The Power
Switch is enabled while the C T Ramp is below COMP as
shown in Figure 35. Once the C T Ramp reaches COMP, the
Power Switch is disabled. If COMP is at the bottom of the
C T Ramp, the converter operates at minimum duty cycle.
While COMP increases, the duty cycle increases, until
COMP reaches the peak of the C T Ramp, at which point the
controller operates at maximum duty cycle.
The C T Charge Signal is filtered through a One Shot Pulse
Generator to set the PWM Latch and enable switching at the
beginning of each period. Switching is allowed while the C T
Ramp is below COMP and a current limit fault is not present.
The PWM Latch and Comparator propagation delay is
typically 150 ns. If the system is designed to operate with a
minimum ON time less than 150 ns, the converter will skip
pulses. Skipping pulses is usually not a problem, unless
operating at a frequency close to the audible range. Skipping
pulses is more likely when operating at high frequencies
during high line and minimum load condition.
A series resistor is included for ESD protection between the
EA output and the COMP pin. Under normal operation, a 220
mV offset is observed between the C T Ramp and the COMP
crossing points. This is not a problem as the series resistor
does not interact with the error amplifier transfer function.
Current Limit Comparator and Power Switch Circuit
The NCP103x monolithically integrates a 200 V Power
Switch Circuit with control logic circuitry. The Power
Switch Circuit is designed to directly drive the converter
recovery time. This spike can cause a premature reset of the
PWM Latch. A proprietary active Leading Edge Blanking
(LEB) Circuit masks the current signal to prevent the
voltage spike from resetting the PWM Latch. The active
LEB masks the current signal until the Power Switch turn
ON transition is complete. The adaptive LEB period
provides better current limit control compared to a fixed
blanking period.
The current limit propagation delay time is typically
100 ns. This time is measured from when an overcurrent
fault appears at the Power Switch Circuit drain, to the start
of the turn--off transition. Propagation delay must be
factored in the transformer design to avoid transformer
saturation.
Thermal Shutdown
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event the maximum
junction temperature is exceeded. When activated, typically
at 150 _ C, the Power Switch Circuit is disabled. Once the
junction temperature falls below 105 _ C, the NCP103x is
allowed to resume normal operation. This feature is
provided to prevent catastrophic failures from accidental
device overheating. It is not intended to be used as a
substitute for proper heatsinking.
Application Considerations
A 2 W bias supply for a 48 V telecom system was designed
using the NCP1030. The bias supply generates an isolated
12 V output. The circuit schematic is shown in Figure 38.
Application Note AND8119/D describes the design of the
bias supply.
transformer. The characteristics of the Power Switch Circuit
are well known. Therefore, the gate drive is tailored to
2.2
1:2.78 MBRA160T3
2.2
control switching transitions and help limit electromagnetic
interference (EMI). The Power Switch Circuit is capable of
switching 200 V.
The Power Switch Circuit incorporates SENSEFET ?
technology to monitor the drain current. A sense voltage is
generated by driving a sense element, R SENSE , with a current
proportional to the drain current. The sense voltage is
compared to an internal reference voltage on the
non--inverting input of the Current Limit Comparator. If the
sense voltage exceeds the reference level, the comparator
+
35--76V
--
0.022
680p
499
NCP1030
GND VDRAIN
CT VCC
VFB UV
COMP OV
1M
45k3
22
MBRA160T3
2.2
+
12V
--
10
4k99
resets the PWM Latch and switching is terminated. The
NCP1030 and NCP1031 drain current limit thresholds are
0.5 A and 1.0 A, respectively.
Each time the Power Switch Circuit turns ON, a narrow
680p
0.033 10k
0.01
34k
0.01
1k30
voltage spike appears across R SENSE . The spike is due to the
Power Switch Circuit gate to source capacitance,
Figure 38. 2 W Isolated Bias Supply Schematic
transformer interwinding capacitance, and output rectifier
http://onsemi.com
15
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| NCP1030EVB | 功能描述:电源管理IC开发工具 NCP1030 EVALUATION BRD RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
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| NCP1031 | 制造商:ONSEMI 制造商全称:ON Semiconductor 功能描述:Low Power PWM Controller with On−Chip Power Switch and Startup Circuits for 48V Telecom Systems |
| NCP1031DR2 | 功能描述:直流/直流开关转换器 Bias Regulator RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
| NCP1031DR2G | 功能描述:直流/直流开关转换器 Bias Regulator w/On Chip Power RoHS:否 制造商:STMicroelectronics 最大输入电压:4.5 V 开关频率:1.5 MHz 输出电压:4.6 V 输出电流:250 mA 输出端数量:2 最大工作温度:+ 85 C 安装风格:SMD/SMT |
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