参数资料
型号: NCP1200P60G
厂商: ON Semiconductor
文件页数: 8/16页
文件大小: 0K
描述: IC CTLR PWM CM 8DIP
标准包装: 50
输出隔离: 隔离
频率范围: 52kHz ~ 70kHz
输入电压: 11 V ~ 16 V
工作温度: -25°C ~ 125°C
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
其它名称: NCP1200P60GOS
NCP1200
1 @ Lp @ Ip 2 @ Fsw + 2.2 W
3. Permanently force the V CC level above V CCH with
an auxiliary winding. It will automatically
disconnect the internal startup source and the IC
will be fully self ? supplied from this winding.
Again, the total power drawn from the mains will
significantly decrease. Make sure the auxiliary
voltage never exceeds the 16 V limit.
Skipping Cycle Mode
The NCP1200 automatically skips switching cycles when
the output power demand drops below a given level. This is
accomplished by monitoring the FB pin. In normal
operation, pin 2 imposes a peak current accordingly to the
load value. If the load demand decreases, the internal loop
asks for less peak current. When this setpoint reaches a
determined level, the IC prevents the current from
decreasing further down and starts to blank the output
pulses: the IC enters the so ? called skip cycle mode, also
named controlled burst operation. The power transfer now
depends upon the width of the pulse bunches (Figure 18 ).
Suppose we have the following component values:
Lp, primary inductance = 1 mH
F SW , switching frequency = 48 kHz
Ip skip = 300 mA (or 350 mV / Rsense)
The theoretical power transfer is therefore:
2
If this IC enters skip cycle mode with a bunch length of
10 ms over a recurrent period of 100 ms, then the total power
transfer is: 2.2 . 0.1 = 220 mW.
To better understand how this skip cycle mode takes place,
a look at the operation mode versus the FB level
immediately gives the necessary insight:
FB
4.8 V
When FB is above the skip cycle threshold (1.4 V by
default), the peak current cannot exceed 1 V/Rsense. When
the IC enters the skip cycle mode, the peak current cannot go
below Vpin1 / 4 (Figure 19). The user still has the flexibility
to alter this 1.4 V by either shunting pin 1 to ground through
a resistor or raising it through a resistor up to the desired
level.
P1
P2
P3
Figure 18. Output pulses at various power levels
(X = 5 m s/div) P1<P2<P3
Max Peak
Current
Skip Cycle
Current Limit
Normal Current Mode Operation
Skip Cycle Operation
3.8 V
1.4 V
Figure 19. The skip cycle takes place at low peak
currents which guarantees noise free operation
Ip min = 350 mV / R sense
Figure 17. Feedback Voltage Variations
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