参数资料
型号: NCP1207BDR2G
厂商: ON Semiconductor
文件页数: 12/17页
文件大小: 0K
描述: IC CTRLR PWM CM OVP OCP HV 7SOIC
标准包装: 1
输出隔离: 隔离
频率范围: 200kHz
输入电压: 10.6 V ~ 20 V
工作温度: -40°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)7 引线
供应商设备封装: 7-SOIC
包装: 标准包装
其它名称: NCP1207BDR2GOSDKR
NCP1207A, NCP1207B
< 550 mW . As we can see, we
P max =
< 7.1 k Ω . The
our case): Rdrop ≤
? IDSS ? Rdrop ? ? DSSduty ? cycle ?
Rdrop
? 7.0 mA ? 7.1 k Ω ? ? 0.286 ?
= = 99.5 mW
will drop at higher operating junction temperatures).
A DIP8 package offers a junction--to--ambient thermal
resistance R θ JA of 100 ? C/W. The maximum power
dissipation can thus be computed knowing the maximum
operating ambient temperature (e.g. 70 ? C) together with
the maximum allowable junction temperature (125 ? C):
Tjmax ? TAmax
R θ JA
do not reach the worse consumption budget imposed by the
operating conditions. Several solutions exist to cure this
trouble:
? The first one consists in adding some copper area around
the NCP1207A DIP8 footprint. By adding a min pad area
of 80 mm 2 of 35 m m copper (1 oz.), R θ JA drops to about
75 ? C/W. Maximum power then grows up to 730 mW.
? A resistor R drop needs to be inserted with pin 8 to a) avoid
negative spikes at turn--off (see below)
b) split the power budget between this resistor and the
package. The resistor is calculated by leaving at least 50 V
on pin 8 at minimum input voltage (suppose 100 Vdc in
Vbulkmin ? 50 V
7.0 mA
power dissipated by the resistor is thus:
Pdrop = VdropRMS 2 ∕ Rdrop
2
=
2
7.1 k Ω
Please refer to the application note AND8069 available
from www.onsemi.com/pub/ncp1200.
? If the power consumption budget is really too high for the
DSS alone, connect a diode between the auxiliary
winding and the V CC pin which will disable the DSS
operation (V CC > 10 V).
The SOIC package offers a 178 ? C/W thermal resistor.
Again, adding some copper area around the PCB footprint
will help decrease this number: 12 mm × 12 mm to drop
R θ JA down to 100 ? C/W with 35 m m copper thickness (1 oz)
or 6.5 mm × 6.5 mm with 70 m m copper thickness (2 oz).
As one can see, we do not recommend using the SO--8
package and the DSS if the part operates at high switching
frequencies. In that case, an auxiliary winding is the best
solution.
Overload Operation
In applications where the output current is purposely not
controlled (e.g. wall adapters delivering raw DC level), it is
interesting to implement a true short--circuit protection. A
short--circuit actually forces the output voltage to be at a low
level, preventing a bias current to circulate in the
Optocoupler LED. As a result, the FB pin level is pulled up
to 4.2 V, as internally imposed by the IC. The peak current
setpoint goes to the maximum and the supply delivers a
rather high power with all the associated effects. Please note
that this can also happen in case of feedback loss, e.g. a
broken Optocoupler. To account for this situation,
NCP1207A hosts a dedicated overload detection circuitry.
Once activated, this circuitry imposes to deliver pulses in a
burst manner with a low duty--cycle. The system recovers
when the fault condition disappears.
During the startup phase, the peak current is pushed to the
maximum until the output voltage reaches its target and the
feedback loop takes over. This period of time depends on
normal output load conditions and the maximum peak
current allowed by the system. The time--out used by this IC
works with the V CC decoupling capacitor: as soon as the
V CC decreases from the VCC OFF level (typically 12 V) the
device internally watches for an overload current situation.
If this condition is still present when the VCC ON level is
reached, the controller stops the driving pulses, prevents the
self--supply current source to restart and puts all the circuitry
in standby, consuming as little as 330 m A typical (I CC3
parameter). As a result, the V CC level slowly discharges
toward 0. When this level crosses 5.3 V typical, the
controller enters a new startup phase by turning the current
source on: V CC rises toward 12 V and again delivers output
pulses at the VCC OFF crossing point. If the fault condition
has been removed before VCC ON approaches, then the IC
continues its normal operation. Otherwise, a new fault cycle
takes place. Figure 24 shows the evolution of the signals in
presence of a fault.
http://onsemi.com
12
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