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| 型号： | NCP1246AD100R2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 37/39页 |
| 文件大小： | 0K |
| 描述： | IC CTLR CURR MODE 100KHZ 8SOIC |
| 标准包装： | 2,500 |
| 系列： | * |
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NCP1246
Latch ? Off Input
Figure 70. Latch Detection Schematic
The Latch pin is dedicated to the latch ? off function: it
includes two levels of detection that define a working
window, between a high latch and a low latch: within these
two thresholds, the controller is allowed to run, but as soon
as either the low or the high threshold is crossed, the
controller is latched off. The lower threshold is intended to
be used with an NTC thermistor, thanks to an internal current
source I NTC .
An active clamp prevents the voltage from reaching the
high threshold if it is only pulled up by the I NTC current. To
reach the high threshold, the pull ? up current has to be higher
than the pull ? down capability of the clamp (typically
1.5 mA at V OVP ).
To avoid any false triggering, spikes shorter than 50 m s
(for the high latch and 65 kHz version) or 350 m s (for the low
latch) are blanked and only longer signals can actually latch
the controller.
Reset occurs when a brown ? out condition is detected or
the V CC is cycled down to a reset voltage, which in a real
application can only happen if the power supply is
unplugged from the ac line.
Upon startup, the internal references take some time
before being at their nominal values; so one of the
comparators could toggle even if it should not. Therefore the
internal logic does not take the latch signal into account
before the controller is ready to start: once V CC reaches
V CC(on) , the latch pin High latch state is taken into account
and the DRV switching starts only if it is allowed; whereas
the Low latch (typically sensing an over temperature) is
taken into account only after the soft ? start is finished. In
addition, the NTC current is doubled to I NTC(SSTART) during
the soft ? start period, to speed up the charging of the Latch
pin capacitor. The maximum value of Latch pin capacitor is
given by the following formula (The standard start ? up
condition is considered and the NTC current is neglected):
C LATCH
max
+
t SSTART
min @ I NTC(SSTART) min
V clamp0 min
+
8.0 @ 10 ? 3 @ 130 @ 10 ? 6
1.0
F + 1.04 m F (eq. 4)
http://onsemi.com
37
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