参数资料
型号: NCP1271P100G
厂商: ON Semiconductor
文件页数: 11/21页
文件大小: 0K
描述: IC CTRLR PWM CM OVP OTP HV 7DIP
标准包装: 1,000
系列: Soft-Skip™
输出隔离: 隔离
频率范围: 85kHz ~ 107kHz
输入电压: 10 V ~ 20 V
工作温度: -40°C ~ 125°C
封装/外壳: 8-DIP(0.300",7.62mm),7 引线
供应商设备封装: 7-PDIP
包装: 管件
NCP1271
cleared after the double hiccup, then the application
restarts. If not, then the process is repeated.
4. Latched Shutdown – When the Skip/latch pin (Pin
1) voltage is pulled above 8.0 V for more than
13 m s, the NCP1271 goes into latchoff shutdown.
The output is held low and V CC stays in hiccup
mode until the latch is reset. The reset can only
occur if Vcc is allowed to fall below V CC(reset)
(4.0 V typical). This is generally accomplished by
unplugging the main input AC source.
5. Non ? Latched Shutdown – If the FB pin is pulled
below the skip level, then the device will enter a
non ? latched shutdown mode. This mode disables
the driver, but the controller automatically recovers
when the pulldown on FB is released. Alternatively,
Vcc can also be pulled low (below 190 mV) to
shutdown the controller. This has the added benefit
of placing the part into a low current consumption
mode for improved power savings.
Biasing the Controller
During startup, the Vcc bias voltage is supplied by the
Startup current
4.1 mA
200 uA
0.6 V V CC(latch) V CC(on) V CC
Figure 23. Startup Current at Various V CC Levels
V CC Double Hiccup Mode
Figure 24 illustrates the block diagram of the startup
circuit. An undervoltage lockout (UVLO) comparator
monitors the V CC supply voltage. If V CC falls below
V CC(off) , then the controller enters “double hiccup mode.”
V bulk
HV
HV Pin (Pin 8). This pin is capable of supporting up to
500 V, so it can be connected directly to the bulk capacitor.
4.1 mA when Vcc > 0.6 V
200 uA when Vcc < 0.6 V
8
Q
S
Internally, the pin connects to a current source which
rapidly charges V CC to its V CC(on) threshold. After this
level is reached, the controller turns on and the transformer
auxiliary winding delivers the bias supply voltage to V CC.
The startup FET is then turned off, allowing the standby
power loss to be minimized. This in ? chip startup circuit
minimizes the number of external components and Printed
Circuit Board (PCB) area. It also provides much lower
power dissipation and faster startup times when compared
to using startup resistors to V CC . The auxiliary winding
needs to be designed to supply a voltage above the V CC(off)
level but below the maximum V CC level of 20 V.
For added protection, the NCP1271 also include a dual
startup mode. Initially, when V CC is below the inhibit
voltage V inhibit (600 mV typical), the startup current source
is small (200 uA typical). The current goes higher (4.1 mA
turn off
UVLO
+
?
R
12.6/
5.8 V
double
hiccup
B 2 9 .1 V
Counter
?
+
&
20V
turn on internal bias
6
Vcc
typical) when V CC goes above V inhibit . This behavior is
illustrated in Figure 23. The dual startup feature protects
the device by limiting the maximum power dissipation
when the V CC pin (Pin 6) is accidentally grounded. This
slightly increases the total time to charge V CC , but it is
generally not noticeable.
Figure 24. V CC Management
During double hiccup operation, the Vcc level falls to
V CC(latch) (5.8 V typical). At this point, the startup FET is
turned back on and charges V CC to V CC(on) (12.6 V typical).
V CC then slowly collapses back to the V CC(latch) level. This
cycle is repeated twice to minimize power dissipation in
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