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参数资料
| 型号： | NCP1271P100G |
| 厂商： | ON Semiconductor |
| 文件页数： | 14/21页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM CM OVP OTP HV 7DIP |
| 标准包装： | 1,000 |
| 系列： | Soft-Skip™ |
| 输出隔离： | 隔离 |
| 频率范围： | 85kHz ~ 107kHz |
| 输入电压： | 10 V ~ 20 V |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm），7 引线 |
| 供应商设备封装： | 7-PDIP |
| 包装： | 管件 |
NCP1271
Rramp +
+ 5.3 k W
43 mV m s
8.1 m A m s
Ramp Compensation
Ramp compensation is a known mean to cure
subharmonic oscillations. These oscillations take place at
half the switching frequency and occur only during
continuous conduction mode (CCM) with a duty ? cycle
greater than 50%. To lower the current loop gain, one
usually injects between 50 and 75% of the inductor down
slope. The NCP1271 generates an internal current ramp
that is synchronized with the clock. This current ramp is
then routed to the CS pin. Figures 32 and 33 depict how the
ramp is generated and utilized. Ramp compensation is
simply formed by placing a resistor, R ramp , between the CS
pin and the sense resistor.
Ramp current, I ramp
100uA
time
(eq. 4)
It is recommended that the value of R ramp be limited to
less then 10 k W . Values larger than this will begin to limit
the effective duty cycle of the controller and may result in
reduced transient response.
Frequency Jittering
Frequency jittering is a method used to soften the EMI
signature by spreading the energy in the vicinity of the main
switching component. The NCP1271 switching frequency
ranges from +7.5% to ? 7.5% of the switching frequency in
a linear ramp with a typical period of 6 ms. Figure 34
demonstrates how the oscillation frequency changes.
Oscillator Frequency
107.5 kHz
100 kHz
0
80% of period
92.5 kHz
100% of period
Figure 32. Internal Ramp Current Source
DRIVE
6 ms
time
Figure 34. Frequency Jittering
(The values are for the 100 kHz frequency option)
Fault Detection
Figure 35 details the timer ? based fault detection
Clock
Current
Ramp
Oscillator
100 m A Peak
CS
R ramp
R sense
circuitry. When an overload (or short circuit) event occurs,
the output voltage collapses and the optocoupler does not
conduct current. This opens the FB pin (pin 2) and V FB is
internally pulled higher than 3.0 V. Since (V FB /3) is greater
than 1 V, the controller activates an error flag and starts a
130 ms timer. If the output recovers during this time, the
timer is reset and the device continues to operate normally.
However, if the fault lasts for more than 130 ms, then the
Figure 33. Inserting a Resistor in Series with the
Current Sense Information brings Ramp Compensation
For the NCP1271, the current ramp features a swing of
100 m A. Over a 65 kHz frequency with an 80% max duty
cycle, that corresponds to an 8.1 m A/ m s ramp. For a typical
flyback design, let’s assume that the primary inductance
driver turns off and the device enters the V CC Double
Hiccup mode discussed earlier. At the end of the double
hiccup, the controller tries to restart the application.
4.8V
(Lp) is 350 m H, the SMPS output is 19 V, the Vf of the
output diode is 1 V and the Np:Ns ratio is 10:1. The OFF
FB 2
V FB
(Vout ) Vf) @ Ns
+ 571 V mH + 571 mA m s (eq. 3)
time primary current slope is given by:
Np
Lp
V FB
3
V SS
+
?
130ms
delay
&
Fault
disable Drv
When projected over an Rsense of 0.1 W (for example),
this becomes or 57 mV/ m s. If we select 75% of the
downslope as the required amount of ramp compensation,
then we shall inject 43 mV/ m s. Therefore, R ramp is simply
equal to:
Softstart
1V max
Figure 35. Block Diagram of Timer ? Based Fault
Detection
http://onsemi.com
14
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