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| 型号： | NCP1351BPG |
| 厂商： | ON Semiconductor |
| 文件页数： | 11/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM PROG CM OTP 8DIP |
| 标准包装： | 50 |
| 输出隔离： | 隔离 |
| 频率范围： | 调节 |
| 输入电压： | 9.5 V ~ 28 V |
| 工作温度： | -25°C ~ 125°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
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NCP1351
Current Sense Resistor
Current Sense Pin
Figure 8. The Voltage on the Current Sense Pin
Below are a few recommendations concerning the wiring
and the PCB layout:
? A small 22 pF capacitor can be placed between the CS
pin and the controller ground. Place it as close as
possible to the controller.
? Do not place the offset resistor in the vicinity of the
sense element, but put it close to the controller as well.
? Regulation by frequency
? The power a flyback converter can deliver relates to the
energy stored in the primary inductance L p and obeys
the following formulae:
Figure 9. The Voltage Across the Sense
Resistor
in this NCP1351 for simplicity and ease of implementation.
Thus, once the peak current has been selected, the feedback
loop automatically reacts to satisfy Equations 5 and 6. The
external capacitor that you connect between pin 2 and
ground (again, place it close to the controller pins) sets the
maximum frequency you authorize the converter to operate
up to. Normalized values for this timing capacitor are
270 pF (65 kHz) and 180 pF (100 kHz). Of course, different
combinations can be tried to design at higher or lower
frequencies. Please note that changing the capacitor value
does not affect the operating frequency at nominal line and
load conditions. Again, the operating frequency is selected
Pout_DCM +
1
2
LP Ipeak2 FSW h
(eq. 5)
by the feedback loop to cope with Equations 5 and 6
definitions.
Pout_CCM + 12 LP(Ipeak2 * Ivalley2)FSW h
(eq. 6)
The feedback current controls the frequency by changing
the timing capacitor end of charge voltage, as illustrated by
V C + 45 k (I FB * 40u) ) 500m (eq. 7)
Where:
h (eta) is the converter efficiency
I peak is the peak inductor current reached at the on time
termination
I valley represents the current at the end of the off time. It
equals zero in DCM.
F SW is the operating frequency.
Thus, to control the delivered power, we can either play on
the peak current setpoint (classical peak current mode
control) or adjust the switching frequency by keeping the
peak current constant. We have chosen the second scheme
Figure 10.
The timing capacitor ending voltage can be precisely
computed using the following formula:
t
Where I FB represents the injected current inside the FB
pin (pin 1). The 40u term corresponds to a 40 mA offset
current purposely placed to force a minimum current
injection when the loop is closed. This allows the controller
to detect a short-circuit condition as the feedback current
drops to zero in that condition.
http://onsemi.com
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