参数资料
型号: NCP1377BDR2G
厂商: ON Semiconductor
文件页数: 9/17页
文件大小: 0K
描述: IC CTRLR PWM SMPS CM UVLO 8SOIC
标准包装: 1
输出隔离: 隔离
频率范围: 300kHz
输入电压: 8.2 V ~ 18 V
工作温度: -40°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SOICN
包装: 标准包装
其它名称: NCP1377BDR2GOSDKR
NCP1377, NCP1377B
Drain
Signal
Timeout
Signal
Demag Restart
Current Sense and Timeout Restart
Drain
Signal
Timeout
Signal
5 m s
5 m s
Figure 20. When the primary natural ringing becomes too low, the internal TimeOut
together with the sense comparator initiates a new cycle when FB passes the skip level.
An optocoupler is generally used to transfer the feedback
information to the FB pin while providing the necessary
isolation. It introduces a limitation in how low the skip
level can be adjusted since an optocoupler cannot pull the
FB voltage below its Vce(sat), which is usually around
150 mV. Therefore, in order to take into account
temperature and process variations, it is not recommended
to set up the skip level below 250 mV, which corresponds
to a minimum resistor Rskip of 420 W . The 150 mV is a
much lower level than what will usually be used (it sets the
peak current when entering skip mode at 5% of the
7.0
maximum peak current). If anyway a lower skip threshold
is needed, care must be taken to select an optocoupler with
a Vce(sat) guaranteed to be below the chosen skip level
with enough margin.
Demagnetization Detection
The core reset detection is done by monitoring the
voltage activity on the auxiliary winding. This voltage
features a FLYBACK polarity. The typical detection level
is fixed at 50 mV as exemplified by Figure 21.
5.0
POSSIBLE
RESTARTS
TO INTERNAL
3.0
COMPARATOR
2
R esd
1
1
5
R dem
4
1.0
? 1.0
0V
50 mV
R int
R esd + R int = 28 k
ESD2
ESD1
4
Aux
3
Figure 21. Core Reset Detection is Done through
a Dedicated Auxiliary Winding Monitoring
http://onsemi.com
9
Figure 22. Internal Pad Implementation
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