参数资料
型号: NCP1378DR2
厂商: ON Semiconductor
文件页数: 9/15页
文件大小: 0K
描述: IC REG CTRLR FLYBACK PWM 8-SOIC
产品变化通告: LTB Notification 03/Jan/2008
标准包装: 2,500
PWM 型: 电流模式
输出数: 1
频率 - 最大: 100kHz
电源电压: 8.2 V ~ 18 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: 0°C ~ 125°C
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
包装: 带卷 (TR)
其它名称: NCP1378DR2OS
NCP1378
Drain
Signal
Timeout
Signal
Demag RESTART
Current Sense and Timeout Restart
Drain
Signal
Timeout
Signal
5 m s
5 m s
Figure 19. When the primary natural ringing becomes too low, the current
sense initiates a new cycle when FB passes the skip level.
An optocoupler is generally used to transfer the feedback
information to the FB pin while providing the necessary
isolation. It introduces a limitation in how low the skip
level can be adjusted since an optocoupler cannot pull the
FB voltage below its Vce(sat), which is usually around
150 mV. Therefore, in order to take into account
temperature and process variations, it is not recommended
to set up the skip level below 250 mV, which corresponds
to a minimum resistor Rskip of 420 Ω . The 150 mV is a
much lower level than what will usually be used (it sets the
peak current when entering skip mode at 5% of the
7.0
maximum peak current). If anyway a lower skip threshold
is needed, care must be taken to select an optocoupler with
a Vce(sat) guaranteed to be below the chosen skip level
with enough margin.
Demagnetization Detection
The core reset detection is done by monitoring the
voltage activity on the auxiliary winding. This voltage
features a FLYBACK polarity. The typical detection level
is fixed at 50 mV as exemplified by Figure 20.
5.0
3.0
POSSIBLE
RESTARTS
TO INTERNAL
COMPARATOR
3
R esd
2k
4
1
5
R dem
2
1.0
--1.0
0V
50 mV
ESD
ESD
4
1
Aux
Figure 20. Core Reset Detection is Done through
a Dedicated Auxiliary Winding Monitoring
http://onsemi.com
9
Figure 21. Internal Pad Implementation
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