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参数资料
| 型号： | NCP1382DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 12/25页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM OVP OTP 14SOIC |
| 标准包装： | 2,500 |
| 输出隔离： | 隔离 |
| 频率范围： | 调节 |
| 输入电压： | 9 V ~ 20 V |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOICN |
| 包装： | 带卷 (TR) |
NCP1381, NCP1382
Figure 12 depicts the internal comparator arrangement.
The FB pin level is permanently compared to a fixed level,
V DD
V skip
Reset
V skip , also available on Pin 5 for adjustment. As a result, the
user can wire a resistor to ground and alter the skip level in
case of noise problems. When the FB pin is above V skip , the
comparator is transparent to the operation. When the load
becomes lighter, the FB level goes down too. When it
reaches V skip , the comparator goes high and resets the
internal flip--flop: the driving pulses are stopped. As a result,
V out starts to also decrease since no energy transfer is
ensured. Detecting a decay in the output voltage, the FB loop
will react by increasing its level. When the level crosses
R
6
30 m A
5
25 k
8
V DD
Soft--Start
Activation
--
+
Hysteresis = 50 mV
V skip plus a slight hysteresis, pulses restart again: a ripple
occurs on the FB pin. Please note that the soft--start will be
activated every time the skip comparator asks to restart.
Therefore, instead of having sharp skip transitions, a smooth
current rampup can be observed on the current envelope.
This option significantly decreases the acoustical noise.
Figure 13 shows a typical shot and Figure 15 portrays
several skip cycles.
Maximum
Peak Current
200
Skip Cycle
Current Limit
100
0
Width
Recurrence
Figure 11. The Skip Cycle Takes Place at Low Peak
Currents Which Guaranties Noise Free Operation
Figure 12. A Resistor to GND can Adjust the Skip
Level
As soon as the feedback voltage goes up again, there can
be two situations as we have seen before: in normal
operating conditions, e.g. when the drain oscillations are
generous, the demagnetization comparator can detect the
45 mV crossing and gives the “green light”, alone, to
reactive the power switch. However, when skip cycle takes
place (e.g. at low output power demands), the restart event
slides along the drain ringing waveforms (actually the valley
locations) which decays more or less quickly, depending on
the L primary --C parasitic network damping factor. The situation
can thus quickly occur where the ringing becomes too weak
to be detected by the demagnetization comparator: it then
permanently stays locked in a given position and can no
longer deliver the “green light” to the controller. To help in
this situation, the NCP1381/82 implements a 8 m s timeout
generator: each time the 45 mV crossing occurs, the timeout
is reset. So, as long as the ringing becomes too low, the
timeout generator starts to count and after 8 m s, it delivers its
“green light”. If the skip signal is already present then the
controller restarts; otherwise the logic waits for it to release
the reset input and set the drive output high. Figure 14
depicts these two different situations:
http://onsemi.com
12
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