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参数资料
| 型号： | NCP1382DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 7/25页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM OVP OTP 14SOIC |
| 标准包装： | 2,500 |
| 输出隔离： | 隔离 |
| 频率范围： | 调节 |
| 输入电压： | 9 V ~ 20 V |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOICN |
| 包装： | 带卷 (TR) |
NCP1381, NCP1382
Startup sequence
When the power supply is first connected to the mains
outlet, the NCP1381/82 starts to consume current. However,
due to a novel architecture, the internal startup current is
kept very low, below 15 m A as a maximum value. The
current delivered by the startup resistor also feeds the V CC
capacitor and its voltage rises. When the voltage on this
capacitor reaches the VCC ON level (typically 15 V), the
controller delivers pulses and increases its consumption. At
this time, the V CC capacitor alone supplies the controller: the
auxiliary supply is supposed to take over before V CC
collapses below VCC OFF . Figure 3 shows the internal
arrangement of this structure:
High Voltage
I total
As soon as V CC reaches 15 V (VCC ON ), driving pulses are
delivered on Pin 9 and the auxiliary winding grows up the
V CC pin. Because the output voltage is below the target (the
SMPS is starting up), the controller smoothly pushes the
peak current to I max (0.8 V / R sense ) which is reached after
5 ms (typical internal soft--start period). After soft--start
completion, the peak current setpoint reaches its maximum
(during the startup period but also anytime a short--circuit
occurs), an internal error flag is asserted, I P Flag, testifying
that the system is pushed to the maximum power (I P = I P
maximum). This flag is used to detect a faulty condition,
where the converter asks for the maximum peak capability
longer than what has been programmed by the designer. The
duration of the faulty condition is actually set up by a
capacitor connected to Pin 4.
Figure 4 shows a portion of this internal arrangement. If
the fault comparator acknowledges for a problem, the
10
I startup
R startup
controller stops all driving pulses and turns--on the internal
I CC3 current--source. This source serves for the latch--off
phase creation, that is to say, forcing the V CC to go down,
despite the presence of the startup current still flowing via
Winding
UVLO
+
--
+
VCC ON
VCC OFF
Auxiliary
+
CV CC
the startup resistor. Therefore, I CC3 should be greater than
I total to ensure proper operation. When V CC reaches a level
of 7 V, I CC3 turns to zero and the startup current can lift V CC
up again. When V CC reaches 15 V, a new attempt is made.
If the fault is still there, pulses last either the timer duration
or are prematurely stopped if a VCC OFF condition occurs
sooner, and a new latchoff phase takes place. If the fault has
8
Figure 3. The Startup Resistor Brings V CC
Above 15 V
gone, the converter resumes operation. Figure 5 portrays the
waveforms obtained during a startup sequence followed by
a fault. One can see the action of the I CC3 source which
creates the latchoff phase and the various resets events on the
timer capacitor in presence of the soft--start end or an aborted
HV
R startup
fault sequence.
Knowing that I timer equals 10 m A, we can calculate the
capacitor needed to reach 4 V in a typical time period.
Suppose we would like a 100 ms fault duration, therefore:
V CC
Management
Latchoff
V CC
10
I CC3
+
CV CC
C timer = 10 m x 100 m / 4 = 250 nF, select a 0.22 m F.
V DD
I timer
Fault
Confirmed
+
--
+
4
C timer
4.0 V
Soft--Start
Soft--Burst
I P Flag
Reset
SW
Figure 4. The Timer Section Uses a Current Source
to Charge Up the Capacitor
http://onsemi.com
7
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