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参数资料
| 型号： | NCP1382DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/25页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM OVP OTP 14SOIC |
| 标准包装： | 2,500 |
| 输出隔离： | 隔离 |
| 频率范围： | 调节 |
| 输入电压： | 9 V ~ 20 V |
| 工作温度： | 0°C ~ 125°C |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOICN |
| 包装： | 带卷 (TR) |
NCP1381, NCP1382
ELECTRICAL CHARACTERISTICS
(For typical values T J = 25 ? C, for min/max values T J = 0 ? C to +125 ? C, V CC = 12 V unless otherwise noted)
Symbol
Rating
Pin
Min
Typ
Max
Unit
GO--TO--STANDBY
R GTS
R skip
V skip
Hyst_ratio
ADJ_GTS
I hyst
Pin 11 Output Impedance (or R dson between Pin 10 and Pin 11 when SW
is Closed)
Skip Adjustment Output Impedance
Default Skip Cycle Level
Ratio Between the Skip Level and the Skip Comparator Hysteresis
Threshold of the ADJ_GTS Comparator
Internal Current Source that Creates an Adjustable Hysteresis to the
ADJ_GTS Comparator
11
5
5
--
1
1
--
17
--
--
220
4.0
15
25
800
3.4
250
5.0
--
35
--
--
280
6.0
Ω
k Ω
mV
--
mV
m A
DEMAGNETIZATION DETECTION BLOCK
V th
V H
VC H
VC L
T dem
C par
R down
T blank
T sw--(min)
Input Threshold Voltage (V pin 3 Decreasing)
Hysteresis (V pin 3 Increasing)
Input Clamp Voltage
High State (I pin 3 = 3.0 mA)
Low State (I pin 3 = --3.0 mA)
DMG Propagation Delay
Internal Input Capacitance at V pin 3 = 1 V
Internal Pulldown Resistor
Internal Blanking Delay after T ON
Frequency Clamp, Minimum (T ON + T OFF )
3
3
3
3
3
3
3
3
--
30
--
9
--0.9
--
--
20
--
7.0
50
30
10
--0.7
200
10
30
3.5
8.0
80
--
12
--0.5
--
--
45
--
9.0
mV
mV
V
V
ns
pF
k Ω
m s
m s
FEEDBACK SECTION
R up
I ratio
Ref
I ref
Internal Pullup Resistor
Pin 6 to Current Setpoint Division Ratio (Maximum V FB = 5 V)
Voltage Reference, I load = 1 mA
Reference Maximum Output Current
6
--
12
12
7.5
--
4.75
10
10
4.0
5.0
--
12.5
--
5.25
--
k Ω
V
mA
PROTECTIONS
V zenlatch
Max tON
I timer
V timfault
T delay
V latchdem
T samp
V CC Limitation in Latched Fault Mode
Maximum On Time Duration
Timer Charging Current
Timer Fault Validation Level
Timeout Before Validating Short--circuit or GTS, C t = 0.22 m F
Latching Level On the Demagnetization Input
Sampling Time for V latchdem Detection after the End of the T ON
10
9
4
4
--
3
3
--
--
7.0
3.5
--
3.7
--
6.0
45
10
4.0
90
4.1
4.0
--
--
13
4.5
--
4.5
--
V
m s
m A
V
ms
V
m s
V latch
Latchoff Level On the Skip Adjustment Pin
NCP1381
NCP1382
5
3.15
2.25
3.5
2.5
3.85
2.75
V
T DELLATCH
VBO high
VBO low
I BO
T SD
TSD hyst
Propagation Delay from Latch Detected to Gate Turned Off (Pin 9
Loaded by 1 nF)
Brown--out Level High
Brown--out Level Low
Brown--out Pin Input Bias Current
Temperature Shutdown, Maximum Value
Hysteresis While in Temperature Shutdown
--
2
2
2
--
--
--
0.45
0.21
--
140
--
220
0.5
0.24
0.04
--
30
--
0.55
0.275
--
--
--
ns
V
V
m A
? C
? C
http://onsemi.com
5
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