参数资料
| 型号： | NCP1393BDR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC HALF BRIDGE DVR HV OSC 8SOIC |
| 标准包装： | 2,500 |
| 类型： | 半桥 |
| 输入类型： | 非反相 |
| 输出数： | 2 |
| 电流 - 峰值输出： | 1A |
| 电源电压： | 16V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
NCP1393B
ELECTRICAL CHARACTERISTICS (For typical values T J = 25 ° C, for min/max values T J = ? 40 ° C to +125 ° C, Max T J = 150 ° C,
V CC = 12 V, unless otherwise noted)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
SUPPLY SECTION
Turn ? On Threshold Level, V CC Going Up
Minimum Operating Voltage after Turn ? On
Startup Voltage on the Floating Section
Cutoff Voltage on the Floating Section
V CC Level at which the Internal Logic gets Reset
Startup Current, V CC < VCC ON , 0 ° C v T amb v +125 ° C
Startup Current, V CC < VCC ON , ? 40 ° C v T amb < 0 ° C
Internal IC Consumption, No Output Load on Pins 8/7 ? 5/4, Fsw = 100 kHz
Internal IC Consumption, 1 nF Output Load on Pins 8/7 ? 5/4, Fsw = 100 kHz
Consumption in Fault Mode (Drivers Disabled, V CC > V CC(min) , R T = 3.5 k W )
Consumption During PFC Delay Period, 0 ° C v T amb v +125 ° C
Consumption During PFC Delay Period, ? 40 ° C v T amb < 0 ° C
Internal IC Consumption, No Output Load on Pin 8/7 F WS = 100 kHz
Internal IC Consumption, 1 nF Output Load on Pin 8/7 F WS = 100 kHz
Consumption in Fault Mode (Drivers Disabled, V boot > Vboot min )
V CC Zener Clamp Voltage @ 20 mA
1
1
1
1
1
1
1
1
1
1
8
8
8
1
VCC ON
VCC min
Vboot ON
Vboot min
VCC reset
I CC
I CC
I CC 1
I CC 2
I CC 3
I CC 4
I CC 4
I boot1
I boot2
I boot3
VCC clamp
10
8
7.8
7
?
?
?
?
?
?
?
?
?
?
?
15.4
11
9
8.8
8
6.5
?
?
2.2
3.4
2.56
?
?
0.3
1.44
0.1
16
12
10
9.8
9
?
50
65
?
?
?
400
470
?
?
?
17.5
V
V
V
V
V
m A
m A
mA
mA
mA
m A
m A
mA
mA
mA
V
INTERNAL OSCILLATOR
Minimum Switching Frequency, R t = 35 k W on Pin 2, D T = 600 ns
Maximum Switching Frequency, R t = 3.5 k W on Pin 2, D T = 600 ns
Reference Voltage for all Current Generations
Internal Resistance Discharging C soft ? start
Operating Duty Cycle Symmetry
2
2
2
2
5, 7
F SW min
F SW max
V ref RT
Rt discharge
DC
24.25
208
3.33
?
48
25
245
3.5
500
50
25.75
282
3.67
?
52
kHz
kHz
V
W
%
NOTE:
Maximum capacitance directly connected to Pin 2 must be under 100 pF.
DRIVE OUTPUT
Output Voltage Rise Time @ CL = 1 nF, 10 ? 90% of Output Signal
Output Voltage Fall Time @ CL = 1 nF, 10 ? 90% of Output Signal
Source Resistance
Sink Resistance
Dead ? Time (Measured Between 50% of Rise and Fall Edge)
Leakage Current on High Voltage Pins to GND (600 Vdc)
5, 7
5, 7
5, 7
5, 7
5,7
6,7,8
T r
T f
R OH
R OL
T_dead
IHV_Leak
?
?
?
?
540
?
40
20
12
5
610
?
?
?
?
?
720
5
ns
ns
W
W
ns
m A
PROTECTION
Brown ? Out Input Bias Current
Brown ? Out Level
Hysteresis Current, V pin3 < VBO
Latching Voltage on BO Pin
Propagation Delay Before Drivers are Stopped
Delay Before Any Driver Restart
Temperature Shutdown
Hysteresis
3
3
3
3
3
?
?
?
IBO bias
V BO
I BO
V latch
EN Delay
PFC Delay
TSD
TSD hyste
?
0.95
15.6
1.9
?
?
140
?
0.01
1
18.2
2
20
100
?
30
?
1.05
20.7
2.1
?
?
?
?
m A
V
m A
V
m s
ms
° C
° C
2. Maximum capacitance directly connected to Pin 2 must be under 100 pF.
http://onsemi.com
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