参数资料
型号: NCP1395ADR2G
厂商: ON Semiconductor
文件页数: 15/27页
文件大小: 0K
描述: IC REG CTRLR PWM VM 16-SOIC
标准包装: 1
PWM 型: 电压模式
输出数: 2
频率 - 最大: 1.11MHz
占空比: 52%
电源电压: 9.3 V ~ 20 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-SOIC(0.154",3.90mm 宽)
包装: 剪切带 (CT)
其它名称: NCP1395ADR2GOSCT
NCP1395A/B
? Finally, Two Circuit Versions, A and B: The A and
B versions differ because of the following changes:
1. The startup thresholds are different, the A starts
to pulse for V CC = 12.8 V whereas the B pulses
for V CC = 10 V. The turn off levels are the
same, however. The A is recommended for
consumer products where the designer can use
an external startup resistor, whereas the B is
Voltage ? Controlled Oscillator
The VCO section features a high ? speed circuitry
allowing an internal operation from 100 kHz up to
2.0 MHz. However, as a division by two internally creates
the two Q and Qbar outputs, the final effective signal on
Vdd
more recommended for industrial/medical
applications where a 12 V auxiliary supply
directly powers the chip.
2. The A version does not activate the soft ? start
upon release of the fast fault input. This is to let
the designer implement skip cycle. To the
opposite, the B version goes back to operation
upon the fast fault pin release via a soft ? start
sequence.
output A and B switches between 50 kHz and 1.0 MHz.
The VCO is configured in such a way that if the feedback
pin goes up, the switching frequency also goes up.
Figure 33 shows the architecture of this oscillator.
FBinternal
+
-
max
Fsw
Fmin
Rt ? m sets
Vref
Imin
0 to I_Fmax
+
-
max
S
D
Clk
Q
Q
Fmin for V(FB) < Vfb_off
Cint
+
R
Vdd
IDT
A
B
DT
Rdt sets
the deadtime
Fmax
Vref
Imin
Vdd
Vcc
Rt ? max sets
the maximum Fsw
FB
Rfb
-
+
Vfb < Vb_fault
start fault timer
20 k
Vb_fault
Figure 33. Simplified VCO Architecture
http://onsemi.com
15
+
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