参数资料
型号: NCP1611BDR2G
厂商: ON Semiconductor
文件页数: 24/29页
文件大小: 879K
描述: IC PFC CTLR HE ENHANCED 8-SOIC
标准包装: 3,000
系列: *
NCP1611
http://onsemi.com
24
Hence, the maximum power that can be delivered by the
PFC stage is:
P
in,avg
max
+
V
in,rms
2
@ T
ON(LL)
2 @ L
at low line
P
in,avg
max
+
V
in,rms
2
@ T
ON(HL)
2 @ L
at high line
Figure 65. PWM circuit and timing diagram.
Figure 66. V
TON
 Processing Circuit. The integrator OA1 amplifies the error between V
REGUL
 and IN1 so that on
average, (V
TON
 * (t
1
+t
2
)/T) equates V
REGUL
.
Remark:
The V
ton
  processing circuit is informed when a
condition possibly leading to a long interruption of the drive
activity (functions generating the STOP signal that disables
the drive  see block diagram  except OCP, i.e., OVP,
OverStress, SKIP, staticOVP and OFF). Otherwise, such
situations would be viewed as a normal deadtime phase and
V
ton
  would inappropriately overdimension V
ton
   to
compensate it. Instead, as illustrated in Figure 66, the V
ton
signal is grounded leading to a short softstart when the
circuit recovers.
Regulation Block and Output Voltage Control
A transconductance error amplifier (OTA) with access to
the inverting input and output is provided. It features a
typical transconductance gain of 200 mS and a maximum
capability of ?0 mA. The output voltage of the PFC stage
is typically scaled down by a resistors divider and monitored
by the inverting input (pin 8). Bias current is minimized
(less than 500 nA) to allow the use of a high impedance
feedback network. However, it is high enough so that the
pin remains in low state if the pin is not connected.
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