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| 型号： | NCP1910B65DWR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 27/37页 |
| 文件大小： | 0K |
| 描述： | IC COMBO CTLR ATX 24-SOIC |
| 标准包装： | 1 |
| 模式： | 连续导电（CCM） |
| 频率 - 开关： | 245 kHz |
| 电流 - 启动： | 100µA |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-SOIC（0.295"，7.50mm 宽）23 引线 |
| 供应商设备封装： | 24-SOIC W |
| 包装： | 标准包装 |
| 其它名称： | NCP1910B65DWR2GOSDKR |
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NCP1910
PFC Power Boost
As depicted in previous section, thanks to the V in2
feed-forward, the power delivery is independent from input
voltage. It brings benefit of good power factor and a direct
control on the frequency foldback. However, in some special
case such as when the ac input voltage drops sharply from
high line to low line, the power will be limited because the
filter on LBO pin slows down the reaction speed to follow
up the change on input voltage. In the end, the bulk voltage
might drop too low and stop the LLC converter.
Hence, NCP1910 builds a so-called PFC power boost
function inside. The idea is to pull down LBO pin to 2 V
typically, V LBO(PD) , when
? V LBO is above 2 V, V LBO(PD) , i.e. the input is at high
line, and
? V CTRL is at maximum for more than timer defined by
t PFCflag , and,
? V bulk is under 95% of nominal output, i.e. VLD is
triggered.
The maximum pulling-down duration is defined by
t LBO(PDlimit) , which is 5 ms typically. A blanking timer,
t LBO(PDblank) , is to avoid this power boost function reacting
V bulk
too soon, which is about 77 ms typically. The PFC power
boost function is inhibited at start-up until bulk voltage is
above 95% of nominal output.
PFC Skip Mode
In order to ensure a proper regulation in no load
conditions, the circuit skips cycles when V CTRL is at its
minimum level. V CTRL is maintained between about 0.6 V
and 3.6 V due to the internal active clamps. A skip sequence
occurs as long as the 0.6 V clamp circuitry is triggered and
switching operations is recovered when the clamp is
inactive.
Fast Transient Response
Given the low bandwidth of the regulation block, the
output voltage of PFC stages may exhibit excessive over or
under ? shoots because of abrupt load or input voltage
variations (such as start ? up duration). As shown in
Figure 52, if the output voltage is out of regulation,
NCP1910 has 2 functions to maintain the output voltage
regulation.
PFC_OK
PFC_OPL
Vdd
R FBU
105% V PREF
+
?
PFC_OVP
I VLD
200 m A
FB
VLD
95% V PREF
C FB
R FBL
V CTRL
V PREF
$ 30 m A
OTA
Figure 52. PFC OVP and VLD
? Over ? Voltage Protection (OVP) : When V FB is higher
than 105% of V PREF (i.e. V bulk > 105% of nominal
bulk voltage), the PFC driver output goes low for
protection. The circuit automatically resumes operation
when V FB becomes lower than 103.2% of V PREF , i.e.
around 44 mV hysteresis in the OVP comparator. If the
nominal V bulk is set at 390 V, then the maximum bulk
?
voltage is 105% of 390 V = 410 V. Hence a cost and
size effective bulk capacitor of lower voltage rating is
suitable for this application,
Voltage ? Low Detection (VLD) : NCP1910 drastically
speeds up the regulation loop by its internal 200 m A
enhanced current source when the bulk voltage is below
95% of its regulation level. Under normal condition, the
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