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| 型号： | NCP1927DR2G |
| 厂商： | ON Semiconductor |
| 文件页数： | 19/24页 |
| 文件大小： | 531K |
| 描述： | IC CTLR PFC/FLYBACK 16-SOIC |
| 标准包装： | 2,500 |
| 系列： | * |
NCP1927
http://onsemi.com
19
Figure 23. Voltage Waveforms for Zero Current
Detection
ZCD Winding
V
ZCD(off)
V
ZCD(on)
V
PDRV
V
drain
V
out
V
CL(POS)
V
ZCD(rising)
V
ZCD(falling)
V
CL(NEG)
V
PZCD
time
time
time
time
During startup, there are no ZCD transitions to enable the
PFC switch. A watchdog timer, t
start
, enables the PFC driver
when no switch pulses are detected before it times out
(180 ms typical). The watchdog timer is also useful while
operating at light load because the amplitude of the ZCD
signal may be too small to cross the ZCD thresholds.
Frequency Clamp
Since the NCP1927 operates in CrM mode over the ac line
half cycle, the switching frequency naturally increases as the
line voltage approaches zero. In order to minimize the PFC
inductor size, the NCP1927 features an internal oscillator
that clamps the maximum switching frequency to f
clamp
(typically 385 kHz).
Overvoltage/Undervoltage Protection
The low bandwidth of the PFC stage feedback network
causes it to have a slow transient response. This increases the
risk of overshoots during transient conditions (startup, load
steps, etc.). For safe operation, overvoltage protection
(OVP) is utilized to prevent the output voltage from rising
too high and overstressing the power stage components. The
NCP1927 detects high V
out
levels and disables the driver
until the output voltage returns to nominal levels. This
protection keeps the output voltage within an acceptable
range.
While traditional PFC controllers often use one single pin
for both under/overvoltage protections and feedback, the
NCP1927 uses a dedicated pin for undervoltage protection
(UVP) and OVP. This configuration allows the
implementation of two separate feedback networks as
shown in Figure 24.
Figure 24. Configuration with Two Separate
Feedback Networks
R
PFB1
R
PFB2
R
POVUV1
R
POVUV2
V
out
PFB
POVUV
The double feedback configuration provides an increased
level of safety, as it protects the PFC stage even if there is a
failure of one of the two feedback arrangements.
A 1 mA (typical) current source, I
UVP
, pulls the POVUV
pin voltage below the UVP threshold if the pin is left floating
to ensure the PFC stage will be protected.
A comparator connected to the POVUV pin provides the
OVP protection. The output voltage that activates the OVP
fault detection is calculated using Equation 13.
V
out(OVP)
+ V
OVP
@
R
POVUV1
) R
POVUV2
R
POVUV2
) I
UVP
@ R
POVUV1
(eq. 13)
where V
out(OVP)
is the peak value of the output voltage
including ripple and V
OVP
is the OVP threshold (2.5 V
typical).
When the OVP comparator is activated, the PFC driver is
immediately turned off. Once the feedback voltage drops
below the hysteresis of V
OVP
(V
OVP(HYS)
), the PFC driver
is reenabled. This helps to limit overshoots on the output
during startup and transient loads. Figure 25 depicts the
operation of the OVP circuitry, while Figure 26 shows the
internal block diagram.
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